Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system
文献类型：期刊论文
| 作者 | Yu, Jian1; Cai, Chang1,2; Ning, Bingxu3; Gao, Shuai2; Liu, Tianqi2; Xu, Liewei1,3; Shen, Mingjie3; Yu, Jun1 |
| 刊名 | MICROELECTRONICS RELIABILITY
 |
| 出版日期 | 2021-11-01 |
| 卷号 | 126页码:7 |
| ISSN号 | 0026-2714 |
| 关键词 | Heavy ions Irradiation Hardened Single event upset |
| DOI | 10.1016/j.microrel.2021.114340 |
| 通讯作者 | Cai, Chang(caichang@fudan.edu.cn) |
| 英文摘要 | This paper addresses the issue of soft error mitigation for Static Random-Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) system in radiation environment to reduce their malfunction and system failure rates in space missions. Seven representative circuits are designed by using the logical resources of SRAMbased FPGA. The accelerator tests investigate that the clock distribution of the Triple Modular Redundancy (TMR) circuits is vital to achieve a high Single Event Upset (SEU) tolerance. The separated DTMR_NEW circuits are proposed to overcome the weakness of the conventional TMR circuits, and a 25x improvement of SEU tolerance for the separated DTMR_NEW circuits are verified. The statistical estimations are desirable for engineers to assess and enhance the SEU tolerance of their designed systems at earlier stages to reduce the time and development costs. |
| 资助项目 | fund of innovative center in China Institute of Atomic Energy[KFZC2020010501] ; fund of Municipal Commission of Economy and Information[GYQJ-2020-1-01] ; State Key Laboratory of ASIC System[2020KF009] ; HIRFL[JIZR20GY002] |
| WOS研究方向 | Engineering ; Science & Technology - Other Topics ; Physics |
| 语种 | 英语 |
| 出版者 | PERGAMON-ELSEVIER SCIENCE LTD |
| WOS记录号 | WOS:000733412800013 |
| 资助机构 | fund of innovative center in China Institute of Atomic Energy ; fund of Municipal Commission of Economy and Information ; State Key Laboratory of ASIC System ; HIRFL |
| 源URL | [http://119.78.100.186/handle/113462/141837]  |
| 专题 | 中国科学院近代物理研究所 |
| 通讯作者 | Cai, Chang |
| 作者单位 | 1.Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China 2.Chinese Acad Sci, Inst Modern Phys, Lanzhou, Peoples R China 3.Shanghai Fudan Microelect Grp, FPGA Dev Dept, Shanghai, Peoples R China |
| 推荐引用方式 GB/T 7714 | Yu, Jian,Cai, Chang,Ning, Bingxu,et al. Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system[J]. MICROELECTRONICS RELIABILITY,2021,126:7. |
| APA | Yu, Jian.,Cai, Chang.,Ning, Bingxu.,Gao, Shuai.,Liu, Tianqi.,...&Yu, Jun.(2021).Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system.MICROELECTRONICS RELIABILITY,126,7. |
| MLA | Yu, Jian,et al."Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system".MICROELECTRONICS RELIABILITY 126(2021):7. |
入库方式： OAI收割
来源：近代物理研究所
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