A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps
文献类型：期刊论文
| 作者 | Zhang, Ling; Yang, Jing; Shi, Cong; Lin, Yingcheng; He, Wei; Zhou, Xichuan; Yang, Xu; Liu, Liyuan; Wu, Nanjian |
| 刊名 | SENSORS
 |
| 出版日期 | 2021 |
| 卷号 | 21期号:18页码:6006 |
| 公开日期 | 2021 |
| 源URL | [http://ir.semi.ac.cn/handle/172111/30795]  |
| 专题 | 半导体研究所_半导体超晶格国家重点实验室 |
| 推荐引用方式 GB/T 7714 | Zhang, Ling; Yang, Jing; Shi, Cong; Lin, Yingcheng; He, Wei; Zhou, Xichuan; Yang, Xu; Liu, Liyuan; Wu, Nanjian. A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps[J]. SENSORS,2021,21(18):6006. |
| APA | Zhang, Ling; Yang, Jing; Shi, Cong; Lin, Yingcheng; He, Wei; Zhou, Xichuan; Yang, Xu; Liu, Liyuan; Wu, Nanjian.(2021).A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps.SENSORS,21(18),6006. |
| MLA | Zhang, Ling; Yang, Jing; Shi, Cong; Lin, Yingcheng; He, Wei; Zhou, Xichuan; Yang, Xu; Liu, Liyuan; Wu, Nanjian."A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps".SENSORS 21.18(2021):6006. |
入库方式： OAI收割
来源：半导体研究所
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