A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector
文献类型：期刊论文
| 作者 | Parkalian, N; Robens, M; Grewing, C; Christ, V; Kruth, A; Liebau, D; Muralidharan, P; Nielinger, D; Roth, C; Yegin, U |
| 刊名 | JOURNAL OF INSTRUMENTATION
 |
| 出版日期 | 2018 |
| 卷号 | 13 |
| 关键词 | Analogue electronic circuits Front-end electronics for detector readout VLSI circuits |
| DOI | 10.1088/1748-0221/13/02/P02010 |
| 文献子类 | Article |
| 英文摘要 | This paper presents a 4 GHz phase locked loop (PLL), which is implemented in a 65 nm standard CMOS process to provide low noise and high frequency sampling clocks for readout electronics to be used in the Jiangmen Underground Neutrino Observatory (JUNO) experiment. Based on the application requirements the target of the design is to find the best compromise between power consumption, area and phase noise for a highly reliable topology. The design implements a novel method for the charge pump that suppresses current mismatch when the PLL is locked. This reduces static phase offset at the inputs of the phase-frequency detector (PFD) that otherwise would introduce spurs at the PLL output. In addition, a technique of amplitude regulation for the voltage controlled oscillator (VCO) is presented to provide low noise and reliable operation. The combination of thin and thick oxide varactor transistors ensures optimum tuning range and linearity over process as well as temperature changes for the VCO without additional calibration steps. The current mismatch at the output of the charge pump for the control voltage at about half the 1V supply voltage is below 0.3% and static phase offset down to 0.25% is reached. The total PLL consumes 18.5mW power at 1.8V supply for the VCO and 1V supply for the other parts. |
| 语种 | 英语 |
| WOS记录号 | WOS:000424627300002 |
| 源URL | [http://ir.ihep.ac.cn/handle/311005/297557]  |
| 专题 | 江门中微子实验 |
| 推荐引用方式 GB/T 7714 | Parkalian, N,Robens, M,Grewing, C,et al. A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector[J]. JOURNAL OF INSTRUMENTATION,2018,13. |
| APA | Parkalian, N.,Robens, M.,Grewing, C.,Christ, V.,Kruth, A.,...&van Waasen, S.(2018).A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector.JOURNAL OF INSTRUMENTATION,13. |
| MLA | Parkalian, N,et al."A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector".JOURNAL OF INSTRUMENTATION 13(2018). |
入库方式： OAI收割
来源：高能物理研究所
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