A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration
文献类型：期刊论文
| 作者 | Cao, Yuan2,3; Liu, Wanyi2,3; Zheng, Yue4; Chen, Shuai3,5; Ye, Jing1,6,7; Qian, Lei2,3; Chang, Chip-Hong8 |
| 刊名 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
 |
| 出版日期 | 2023-09-26 |
| 页码 | 14 |
| ISSN号 | 1549-8328 |
| 关键词 | Entropy Authentication System-on-chip Protocols Jitter Computer architecture Rail to rail outputs True random number generator physical unclonable function current-starved ring oscillator |
| DOI | 10.1109/TCSI.2023.3316890 |
| 英文摘要 | True random number generator (TRNG) and physical unclonable function (PUF) have been extensively used to secure low-cost Internet of Things (IoT) endpoints. In this paper, a lightweight reconfigurable TRNG and PUF unified design for custom chip implementation is proposed. The reconfigurable structure consists of a pair of ring oscillators (ROs) with interposed multi-way switches for RO length reconfiguration and shared counters for on-chip calibration. Jitter noise of ROs and metastability of arbiter are harmonized for TRNG operation, while process variations of ROs are extracted for PUF operation. The conflicting requirements on frequency deviation for the randomness of TRNG and the reliability of PUF are resolved by an on-chip calibrator, which automatically selects and stores a challenge with a small frequency difference in TRNG mode upon manufacturing and masks unreliable challenges with large frequency difference during PUF enrollment. Leveraging the advantage of custom chip design, the basic delay cell of the reconfigurable ROs is realized by current starved inverter in weak inversion to minimize the power consumption, increase the jitter, and avail its larger process variation. A new lightweight secure mutual authentication protocol is also proposed to effectively thwart machine learning, replay and man-in-the-middle attacks using only the underlying TRNG and PUF without requiring any other security primitives. The proposed TRNG-PUF design is prototyped with a standard 40 nm 1.1 V CMOS process. It occupies a small footprint of 24,316 mu m(2) . Measured results of the packaged chips show an average energy efficiency of 7.42 pJ/bit in TRNG operation and 0.10 pJ/bit in PUF operation. The bitstreams generated by the test chips passed NIST SP 800-22 and 90B tests, autocorrelation test, and FFT test. |
| 资助项目 | Ministry of Education, Singapore[MOE-T2EP50220-0003] ; Fundamental Research Funds for Natural Science Foundation of Jiangsu Province[BK20191160] ; Open Research of the State Key Laboratory of Computer Architecture[CARCH201901] ; QingLan Project, Changzhou Science and Technology Program[CJ20200071] ; QingLan Project, Changzhou Science and Technology Program[2020029] ; National Natural Science Foundation of China[62274056] ; Open Fund of Advanced Cryptography and System Security Key Laboratory of Sichuan Province[SKLACSS-202209] ; Key Research and Development Program of Jiangsu Province[BE2022098] ; Postdoctoral Science Foundation of Jiangsu Province[2021K605C] ; Ministry of Education, Singapore[MOE-T2EP50220-0003] ; Fundamental Research Funds for Natural Science Foundation of Jiangsu Province[BK20191160] ; Open Research of the State Key Laboratory of Computer Architecture[CARCH201901] ; QingLan Project, Changzhou Science and Technology Program[CJ20200071] ; QingLan Project, Changzhou Science and Technology Program[2020029] ; National Natural Science Foundation of China[62274056] ; Open Fund of Advanced Cryptography and System Security Key Laboratory of Sichuan Province[SKLACSS-202209] ; Key Research and Development Program of Jiangsu Province[BE2022098] ; Postdoctoral Science Foundation of Jiangsu Province[2021K605C] |
| WOS研究方向 | Engineering |
| 语种 | 英语 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| WOS记录号 | WOS:001078373800001 |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/21135]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Zheng, Yue; Chang, Chip-Hong |
| 作者单位 | 1.CASTEST Co, Beijing 100190, Peoples R China 2.Hohai Univ, Coll Internet Things Engn, Changzhou 213022, Peoples R China 3.Rock Solid Secur Lab, Suzhou 215000, Peoples R China 4.Chinese Univ Hong Kong, Sch Sci & Engn, Shenzhen 518172, Peoples R China 5.Binary Semicond Co Ltd, Rock Solid Secur Lab, Suzhou 215000, Peoples R China 6.Chinese Acad Sci, Inst Comp Technol, State Key Lab Proc, Beijing 100045, Peoples R China 7.Univ Chinese Acad Sci, Beijing 101408, Peoples R China 8.Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore |
| 推荐引用方式 GB/T 7714 | Cao, Yuan,Liu, Wanyi,Zheng, Yue,et al. A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2023:14. |
| APA | Cao, Yuan.,Liu, Wanyi.,Zheng, Yue.,Chen, Shuai.,Ye, Jing.,...&Chang, Chip-Hong.(2023).A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,14. |
| MLA | Cao, Yuan,et al."A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2023):14. |
入库方式： OAI收割
来源：计算技术研究所
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