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Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses

文献类型：期刊论文

作者Chu, Cheng2; Liu, Cheng3; Xu, Dawen4; Wang, Ying3; Luo, Tao1; Li, Huawei3; Li, Xiaowei3
刊名ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
出版日期2023-07-01
卷号28期号:4页码:23
关键词Deformable convolution network neural network accelerator irregular memory access runtime tile scheduling
ISSN号1084-4309
DOI10.1145/3597431
英文摘要Deformable convolution networks (DCNs) proposed to address image recognition with geometric or photometric variations typically involve deformable convolution that convolves on arbitrary locations of input features. The locations change with different inputs and induce considerable dynamic and irregular memory accesses that cannot be handled by classic neural network accelerators (NNAs). Moreover, bilinear interpolation (BLI) operation, which is required to obtain deformed features in DCNs, also cannot be deployed on existing NNAs directly. Although a general purposed processor (GPP) seated along with classic NNAs can process the deformable convolution, the processing on GPP can be extremely slow due to the limited parallel computing capability and massive additional data movement. To address the problem, we develop a DCN accelerator on existing NNAs to support both the standard convolution and deformable convolution. Specifically, for the dynamic and irregular accesses in DCNs, we have both the input and output features divided into tiles and build a tile dependency table (TDT) to track the irregular tile dependency at runtime. With the TDT, we further develop an on-chip tile scheduler to handle the dynamic and irregular accesses efficiently. In addition, we propose a novel mapping strategy to enable parallel BLI processing on NNAs and apply layer fusion techniques for more energy-efficient DCN processing. According to our experiments, the proposed accelerator achieves orders of magnitude higher performance and energy efficiency compared to the typical computing architectures including ARM, ARM+TPU, and GPU with 6.6% chip area penalty to a classic NNA.
资助项目National Key R&D Program of China[2022YFB4500405] ; National Natural Science Foundation of China[62174162] ; Singapore Government's Research, Innovation and Enterprise 2020 Plan (Advanced Manufacturing and Engineering domain)[A1687b0033]
WOS研究方向Computer Science
语种英语
WOS记录号WOS:001035842400020
出版者ASSOC COMPUTING MACHINERY
源URL[http://119.78.100.204/handle/2XEOYT63/21299]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Liu, Cheng
作者单位1.ASTAR, Inst High Performance Comp, Singapore 138632, Singapore
2.Indiana Univ, Bloomington, IN 47408 USA
3.Chinese Acad Sci, Inst Comp Technol, Beijing 100180, Peoples R China
4.Hefei Univ Technol, Hefei 230009, Anhui, Peoples R China
推荐引用方式
GB/T 7714		 Chu, Cheng,Liu, Cheng,Xu, Dawen,et al. Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses[J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,2023,28(4):23.
APA Chu, Cheng.,Liu, Cheng.,Xu, Dawen.,Wang, Ying.,Luo, Tao.,...&Li, Xiaowei.(2023).Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,28(4),23.
MLA Chu, Cheng,et al."Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses".ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 28.4(2023):23.

入库方式： OAI收割

来源：计算技术研究所

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