A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner
文献类型：期刊论文
| 作者 | Gao Zhuo; Yang Zongren; Zhao Ying; Yang Yi; Zhang Lu; Huang Lingyi; Hu Weiwu |
| 刊名 | 半导体学报
 |
| 出版日期 | 2009 |
| 卷号 | 000期号:004页码:104 |
| 关键词 | 接收器 CDR 有限元 Gb 校准 元组 CMOS工艺 时钟数据恢复 |
| ISSN号 | 1674-4926 |
| 英文摘要 | This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery （CDR） circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer （CTLE） and decision feedback equalizer （DFE）. |
| 语种 | 英语 |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/36245]  |
| 专题 | 中国科学院计算技术研究所期刊论文_中文 |
| 作者单位 | 中国科学院计算技术研究所 |
| 推荐引用方式 GB/T 7714 | Gao Zhuo,Yang Zongren,Zhao Ying,et al. A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner[J]. 半导体学报,2009,000(004):104. |
| APA | Gao Zhuo.,Yang Zongren.,Zhao Ying.,Yang Yi.,Zhang Lu.,...&Hu Weiwu.(2009).A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner.半导体学报,000(004),104. |
| MLA | Gao Zhuo,et al."A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner".半导体学报 000.004(2009):104. |
入库方式： OAI收割
来源：计算技术研究所
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