中国科学院机构知识库网格
Chinese Academy of Sciences Institutional Repositories Grid
首页 机构 成果 学者
  
  1. CAS IR Grid
  2. 西安光学精密机械研究所
  3. 中国科学院西安光学精密机械研究所
  4. 瞬态光学技术国家重点实验室
A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS

文献类型：期刊论文

作者Ma, Shuaizhe4; Yin, Zhenyu4; Ran, Nianquan4; Xia, Yifei4; Yang, Ruixuan4; Yu, Chuanhao4; Xu, Songqin4; Wang, Binhao3; Qi, Nan2; Zhang, Bing4
刊名IEEE Solid-State Circuits Letters
出版日期2024
卷号7页码:50-53
ISSN号25739603
关键词100-Gb/s PAM-4 CMOS linearity low noise transimpedance amplifier (TIA)
DOI10.1109/LSSC.2024.3351683
产权排序2
英文摘要

This letter presents a 100-Gb/s CMOS PAM-4 transimpedance amplifier (TIA) with multimilliampere maximum linear input current. A low-noise high-linearity TIA architecture is proposed, leveraging the reconfigurable front-end (FE) TIA and the continuous time linear equalizer (CTLE) synced at multiple gain modes. Implemented in a 28-nm CMOS technology, the TIA achieves bandwidth of more than 24 GHz with transimpedance gain of 65 dB Ω, while showing an acrlong IRN current density of 10.4 pA/ √ Hz. The maximum linear input current reaches 2.2 mApp and the total harmonic distortion (THD) is less than 3% for an output swing of 600 mVpp, diff. The chip consumes power of 56 mW from 1.4 and 1.1-V supply. © 2018 IEEE.

语种英语
出版者Institute of Electrical and Electronics Engineers Inc.
源URL[http://ir.opt.ac.cn/handle/181661/97158]  
专题西安光学精密机械研究所_瞬态光学技术国家重点实验室
通讯作者Li, Dan
作者单位1.Beijing University of Posts and Telecommunications, State Key Laboratory of Information Photonics and Optical Communications, School of Integrated Circuits, Beijing; 100876, China
2.Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing; 100083, China;
3.Institute of Optics and Precision Mechanics, University of Chinese Academy of Sciences, Xi'an; 710119, China;
4.Xi'an Jiaotong University, Faculty of Electronic and Information Engineering, Xi'an; 710000, China;
推荐引用方式
GB/T 7714		 Ma, Shuaizhe,Yin, Zhenyu,Ran, Nianquan,et al. A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS[J]. IEEE Solid-State Circuits Letters,2024,7:50-53.
APA Ma, Shuaizhe.,Yin, Zhenyu.,Ran, Nianquan.,Xia, Yifei.,Yang, Ruixuan.,...&Li, Dan.(2024).A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS.IEEE Solid-State Circuits Letters,7,50-53.
MLA Ma, Shuaizhe,et al."A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS".IEEE Solid-State Circuits Letters 7(2024):50-53.

入库方式： OAI收割

来源：西安光学精密机械研究所

浏览0
下载0
收藏0
其他版本

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。