In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays
文献类型：期刊论文
| 作者 | Hui, Yajuan4,5; Li, Qingzhen4,5; Wang, Leimin4,5; Liu, Cheng3; Zhang, Deming2; Miao, Xiangshui1 |
| 刊名 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
 |
| 出版日期 | 2024-01-12 |
| 页码 | 8 |
| 关键词 | In-memory computing majority gates voltage-gated SOT-MRAM Wallace tree multiplier |
| ISSN号 | 1063-8210 |
| DOI | 10.1109/TVLSI.2024.3350151 |
| 英文摘要 | In-memory computing represents an efficient paradigm for high-performance computing using crossbar arrays of emerging nonvolatile devices. While various techniques have emerged to implement Boolean logic in memory, the latency of arithmetic circuits, particularly multipliers, significantly increases with bit-width. In this work, we introduce an in-memory Wallace tree multiplier based on majority gates within voltage-gated spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) crossbar arrays. By utilizing a resistance sum, the majority gate is implemented during READ operations in voltage-gated SOT-MRAM crossbar arrays, resulting in reduced read currents and improved energy efficiency. We employ a series of READ and WRITE operations to perform multiplier calculations, leveraging the fast READ and WRITE speeds of voltage-gated SOT-MRAM devices. Furthermore, the use of five-input majority gates simplifies multiplication by employing uniform logic gates and reducing logic depth, thereby lowering the operation's complexity and the total number of occupied cells. Our experimental results demonstrate that the proposed in-memory Wallace tree multipliers consume three times less energy for in-memory operations than previously reported 4 X 4 multipliers. Moreover, the proposed method reduces the delay overhead from O ( n(2) ) to O ( log2(n) ), where n represents the number of bits. |
| 资助项目 | National Natural Science Foundation of China |
| WOS研究方向 | Computer Science ; Engineering |
| 语种 | 英语 |
| WOS记录号 | WOS:001165589700001 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/38832]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Hui, Yajuan |
| 作者单位 | 1.Huazhong Univ Sci & Technol, Sch Integrated Circuits, Wuhan 430074, Peoples R China 2.Beihang Univ, Sch Integrated Circuit Sci & Engn, Beijing 100191, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100080, Peoples R China 4.China Univ Geosci, Engn Res Ctr Intelligent Technol Geoexplorat, Minist Educ, Wuhan 430074, Peoples R China 5.China Univ Geosci, Hubei Key Lab Adv Control & Intelligent Automation, Wuhan 430074, Peoples R China |
| 推荐引用方式 GB/T 7714 | Hui, Yajuan,Li, Qingzhen,Wang, Leimin,et al. In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2024:8. |
| APA | Hui, Yajuan,Li, Qingzhen,Wang, Leimin,Liu, Cheng,Zhang, Deming,&Miao, Xiangshui.(2024).In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,8. |
| MLA | Hui, Yajuan,et al."In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2024):8. |
入库方式： OAI收割
来源：计算技术研究所
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