Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture
文献类型：期刊论文
| 作者 | Yang, Yinghao3; Lu, Hang1,2,3; Li, Xiaowei1,2,3 |
| 刊名 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
 |
| 出版日期 | 2023-12-01 |
| 卷号 | 42期号:12页码:4749-4762 |
| 关键词 | FPGA accelerator fully homomorphic encryption (FHE) near data processing (NDP) privacy computing |
| ISSN号 | 0278-0070 |
| DOI | 10.1109/TCAD.2023.3292211 |
| 英文摘要 | With the development of the important solution for privacy computing-fully homomorphic encryption (FHE), the explosion of data size, and computing intensity in FHE applications brings enormous challenges to the hardware design. In this article, we propose a novel co-design scheme for FHE acceleration named "Poseidon-NDP," which focuses on improving the efficiency of the hardware resource and the bandwidth. Specifically, we investigate the special implications of the hardware imposed by the FHE applications. It empirically shows that the FHE performance is suffered from both the intractable data movement and the computation bottleneck. Besides, we also introduce the opportunity and the challenges of accelerating FHE on near data processing (NDP) architecture. Based on such analysis, we propose an optimized technique called "NTT-fusion" to simplify the FHE operator and reduce its hardware overhead. Then, we design the accelerator based on the simplified operator to achieve maximized data and computation parallelism with limited hardware resources. Additionally, we evaluate Poseidon-NDP with 4 domain-specific FHE applications on the SmartSSD, which is a practical NDP device. The empirical studies show that the efficient co-design enables Poseidon-NDP vastly superior to the state-of-the-art FHE acceleration techniques: 1) up to 217x/84x speedup over CPU and high-performance GPUs for the number theoretic transform; 2) up to 3.7x/29x higher-speedup/energy delay product (EDP) over the SOTA FPGA accelerator for the FHE applications; and 3) up to 4.9x higher-bandwidth utilization over CPU due to the NDP-based architecture. |
| 资助项目 | National Natural Science Foundation of China |
| WOS研究方向 | Computer Science ; Engineering |
| 语种 | 英语 |
| WOS记录号 | WOS:001123254100033 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/38848]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Lu, Hang |
| 作者单位 | 1.Shanghai Innovat Ctr Processor Technol, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100190, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, Beijing 100045, Peoples R China |
| 推荐引用方式 GB/T 7714 | Yang, Yinghao,Lu, Hang,Li, Xiaowei. Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2023,42(12):4749-4762. |
| APA | Yang, Yinghao,Lu, Hang,&Li, Xiaowei.(2023).Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,42(12),4749-4762. |
| MLA | Yang, Yinghao,et al."Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 42.12(2023):4749-4762. |
入库方式： OAI收割
来源：计算技术研究所
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