A hardware-friendly logarithmic quantization method for CNNs and FPGA implementation
文献类型：期刊论文
| 作者 | Jiang, Tao2,3 ; Xing, Ligang1; Yu, Jinming1; Qian, Junchao1,2,3
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| 刊名 | JOURNAL OF REAL-TIME IMAGE PROCESSING
 |
| 出版日期 | 2024-08-01 |
| 卷号 | 21 |
| 关键词 | Convolution neural networks CNN quantization Hardware accelerator FPGA |
| ISSN号 | 1861-8200 |
| DOI | 10.1007/s11554-024-01484-y |
| 通讯作者 | Yu, Jinming(sdyujinming@163.com) ; Qian, Junchao(qianjunchao@hmfl.ac.cn) |
| 英文摘要 | Convolutional Neural Networks (CNNs) have been widely used in various fields due to their high accuracy and efficiency. The performance of CNNs is mainly affected by the computing capability, memory bandwidth, and flexibility of embedded devices. The high energy efficiency, computing capability, and reconfigurability of FPGAs make it a good platform for hardware acceleration in the design of CNNs. However, the increase of complexity of CNNs, requires memory while the FPGA on-chip storage is limited. Therefore, we use an improved logarithmic quantization to compress the model. This approach allows for significant reduction in bit widths while maintaining high accuracy levels, making it an effective compression method. In this work, a hardware-friendly quantization scheme is proposed, in which the weights use improved logarithmic quantization scheme, and the quantization scheme of activations use the fixed-point-to-logarithmic. The results show that the quantization model has negligible Top-1/5 accuracy loss without any retraining. In addition, we implement an acceleration engine for a heterogeneous Generalized Matrix Multiplication (GEMM) core on Zynq XC7Z020. In GEMM, the multiplier is replaced by logic shifters and adders, which achieves efficient utilization of LUT resources. We use the optimal quantization model on Zynq XC7Z020. The throughput reaches 69.7 GOPs with a power consumption of 6.008W, and the resource efficiency is 8.713 GOPs/DSP or 5.564 GOPs/kLUTs. |
| 资助项目 | National Natural Science Foundation of China |
| WOS研究方向 | Computer Science ; Engineering ; Imaging Science & Photographic Technology |
| 语种 | 英语 |
| WOS记录号 | WOS:001243615300001 |
| 出版者 | SPRINGER HEIDELBERG |
| 资助机构 | National Natural Science Foundation of China |
| 源URL | [http://ir.hfcas.ac.cn:8080/handle/334002/136218]  |
| 专题 | 中国科学院合肥物质科学研究院 |
| 通讯作者 | Yu, Jinming; Qian, Junchao |
| 作者单位 | 1.Shandong First Med Univ & Shandong Acad Med Sci, Shandong Univ, Shandong Canc Hosp & Inst, Dept Radiat Oncol,Sch Med, Jinan 250117, Peoples R China 2.Chinese Acad Sci, Hefei Canc Hosp, Inst Hlth & Med Technol, Hefei Inst Phys Sci,Anhui Prov Key Lab Med Phys &, Hefei 230031, Peoples R China 3.Anhui Jianzhu Univ, Sch Elect & Informat Engn, Dept Elect Sci & Technol, Hefei 230601, Peoples R China |
| 推荐引用方式 GB/T 7714 | Jiang, Tao,Xing, Ligang,Yu, Jinming,et al. A hardware-friendly logarithmic quantization method for CNNs and FPGA implementation[J]. JOURNAL OF REAL-TIME IMAGE PROCESSING,2024,21. |
| APA | Jiang, Tao,Xing, Ligang,Yu, Jinming,&Qian, Junchao.(2024).A hardware-friendly logarithmic quantization method for CNNs and FPGA implementation.JOURNAL OF REAL-TIME IMAGE PROCESSING,21. |
| MLA | Jiang, Tao,et al."A hardware-friendly logarithmic quantization method for CNNs and FPGA implementation".JOURNAL OF REAL-TIME IMAGE PROCESSING 21(2024). |
入库方式： OAI收割
来源：合肥物质科学研究院
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