JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits
文献类型：期刊论文
| 作者 | Fu, Rongliang2; Zhou, Minglei1; Chen, Siyan3; Chen, Xinda3; Huang, Junying1; Ye, Xiaochun1; Zhang, Zhimin1; Ho, Tsung-Yi2 |
| 刊名 | IEEE TRANSACTIONS ON COMPUTERS
 |
| 出版日期 | 2026 |
| 卷号 | 75期号:1页码:290-304 |
| 关键词 | Logic gates Routing Circuits Clocks Physical design Delays Logic Trees (botanical) Switches Layout Superconducting electronics single-flux-quantum placement routing length-matching clock-aware |
| ISSN号 | 0018-9340 |
| DOI | 10.1109/TC.2025.3625822 |
| 英文摘要 | Superconducting rapid single-flux-quantum (RSFQ) logic is a promising candidate for advancing future computing technologies due to its low-energy consumption and high-frequency capabilities. However, precise timing alignment is crucial for its physical design, posing significant challenges in length-matching placement and routing. This paper introduces JPnR, a physical design framework tailored for RSFQ circuits, featuring a clock-aware length-matching placer and a length-matching multi-terminal router. The placer simultaneously considers both clock distribution and timing constraints, distributing clock pulses heuristically and transforming the placement problem into a single-source shortest-path problem. This allows it to minimize vertical wirelength using dynamic programming and iteratively optimize placement via a barycenter-like reordering method. The router tackles challenges related to splitter placement and length-matching multi-terminal routing using a two-layer planar Manhattan routing model. Initial routing assigns tracks based on the left-edge algorithm to minimize routing width while employing the dogleg algorithm to resolve cycles in the vertical constraint graph. Length-matching is achieved via a splitter tree-based hierarchical approach with maximum-flow-based detour insertion. Finally, a PTL region expansion strategy is employed for unsatisfied connections. Experimental results on RSFQ benchmarks demonstrate the effectiveness and efficiency of JPnR. |
| 资助项目 | JC STEM Lab of Intelligent Design Automation through The Hong Kong Jockey Club Charities Trust ; Research Grants Council of Hong Kong SAR[CUHK14207523] ; National Natural Science Foundation of China[62302477] ; State Key Lab of Processors, Institute of Computing Technology, CAS[CLQ202402] ; Shandong Province Natural Science Foundation, China[ZR2024MF073] |
| WOS研究方向 | Computer Science ; Engineering |
| 语种 | 英语 |
| WOS记录号 | WOS:001635821300001 |
| 出版者 | IEEE COMPUTER SOC |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/42833]  |
| 专题 | 中国科学院计算技术研究所 |
| 通讯作者 | Huang, Junying |
| 作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, SKLP, Beijing 100190, Peoples R China 2.Chinese Univ Hong Kong, Dept Comp Sci & Engn, Hong Kong 999077, Peoples R China 3.ShanghaiTech Univ, Shanghai 201210, Peoples R China |
| 推荐引用方式 GB/T 7714 | Fu, Rongliang,Zhou, Minglei,Chen, Siyan,et al. JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits[J]. IEEE TRANSACTIONS ON COMPUTERS,2026,75(1):290-304. |
| APA | Fu, Rongliang.,Zhou, Minglei.,Chen, Siyan.,Chen, Xinda.,Huang, Junying.,...&Ho, Tsung-Yi.(2026).JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits.IEEE TRANSACTIONS ON COMPUTERS,75(1),290-304. |
| MLA | Fu, Rongliang,et al."JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits".IEEE TRANSACTIONS ON COMPUTERS 75.1(2026):290-304. |
入库方式： OAI收割
来源：计算技术研究所
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