DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme
文献类型：期刊论文
| 作者 | Liu, Tianyu1,2; Fan, Zhihua1,2; Li, Wenming1,2; Wang, Zhen1,2; Qiu, Yuhang1,2; Tang, Shengzhong1,2; Wu, Haibin1,2; Liu, Yanhuan1,2; Ye, Xiaochun1,2; Fan, Dongrui1,2 |
| 刊名 | ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
 |
| 出版日期 | 2025-12-01 |
| 卷号 | 22期号:4页码:26 |
| 关键词 | CGRA hardware-software co-design network-on-chip |
| ISSN号 | 1544-3566 |
| DOI | 10.1145/3773768 |
| 英文摘要 | Coarse-Grained Reconfigurable Architectures (CGRAs) have been regarded as promising spatial computing fabric for the ever-evolving algorithms in multiple domains. However, pure software scheduling cannot compensate for the deficiencies in over-serialization and load imbalancing of these pure static CGRA designs. To address the issues caused by limited hardware flexibility, an in-depth study on the balance between the software and hardware scheduling design of CGRA is needed to achieve more precise, accurate, and adaptive scheduling of dataflow. In this article, we propose DFGAS (DFG-Aware Scheduling), a dataflow-driven CGRA which provides a comprehensive scheduling approach that encompasses software prediction, runtime adaptive execution, and post-execution refinement. Prior to execution, the TimeStamp prediction algorithm, coupled with the inherent dataflow execution model, enables coarse-grained (block-level) prediction for prioritized transfer and computation on NoC and PEs. During execution, the execution of key dataflow graph (DFG) blocks and edges is accelerated by incorporating a dynamic and adaptive dataflow mechanism. It leverages hardware-software co-design to obtain a holistic view of the entire DFG and continuously self-adaptively optimizes the scheduling process. Furthermore, a complete workflow is implemented, supporting making refinements to the software DFG mapping results. DFGAS represents a scheduling scheme of CGRA that is worth exploring, achieving hardware-software co-design that balances energy efficiency and flexibility. Experiments show that DFGAS achieves 1.35x energy efficiency improvement over a dataflow-driven CGRA and 1.9x energy efficiency improvement over a state-of-the-art pure static CGRA. |
| 资助项目 | National Key R&D Program of China[2023YFB4503500] ; CAS Project for Young Scientists in Basic Research[YSBR-029] ; CAS Project for Youth Innovation Promotion Association ; Beijing Natural Science Foundation[L234078] ; Beijing Nova Program[20220484054] ; Beijing Nova Program[20230484420] |
| WOS研究方向 | Computer Science |
| 语种 | 英语 |
| WOS记录号 | WOS:001667494000010 |
| 出版者 | ASSOC COMPUTING MACHINERY |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/42887]  |
| 专题 | 中国科学院计算技术研究所 |
| 通讯作者 | Fan, Zhihua; Li, Wenming |
| 作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing, Peoples R China 2.Univ Chinese Acad Sci, Sch Comp Sci & Technol, Beijing, Peoples R China |
| 推荐引用方式 GB/T 7714 | Liu, Tianyu,Fan, Zhihua,Li, Wenming,et al. DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme[J]. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION,2025,22(4):26. |
| APA | Liu, Tianyu.,Fan, Zhihua.,Li, Wenming.,Wang, Zhen.,Qiu, Yuhang.,...&Fan, Dongrui.(2025).DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme.ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION,22(4),26. |
| MLA | Liu, Tianyu,et al."DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme".ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 22.4(2025):26. |
入库方式： OAI收割
来源：计算技术研究所
浏览0
下载0
收藏0
其他版本
除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。