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AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models

文献类型：期刊论文

作者Li, Cangyuan2,3; Chen, Chujie3,4; Pan, Yudong2; Xu, Wenjun3,4; Liu, Yiqi3,5; Chang, Kaiyan3,6; Wang, Yujie2; Wang, Mengdi2; Li, Huawei1,7; Han, Yinhe2,8
刊名ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
出版日期2025-11-01
卷号30期号:6页码:21
关键词Verilog code generation LLM agent verilog
ISSN号1084-4309
DOI10.1145/3737286
英文摘要Hardware description language (HDL) code designing is a critical component of the chip design process, requiring substantial engineering and time resources. Recent advancements in large language models (LLMs), such as GPT series, have shown promise in automating HDL code generation. However, current LLM-based approaches face significant challenges in meeting real-world hardware design requirements, particularly in handling complex designs and ensuring code correctness. Our evaluations reveal that the functional correctness rate of LLM-generated HDL code significantly decreases as design complexity increases. In this article, we propose the AutoSilicon framework, which aims to scale up the hardware design capability of LLMs. AutoSilicon incorporates an agent system, which (1) allows for the decomposition of large-scale, complex code design tasks into smaller, simpler tasks; (2) provides a compilation and simulation environment that enables LLMs to compile and test each piece of code it generates; and (3) introduces a series of optimization strategies. Experimental results demonstrate that AutoSilicon can scale hardware designs to projects with code equivalent to over 10,000 tokens. In terms of design quality, it further improves the syntax correctness rate and functional correctness rate compared with approaches that do not employ any extensions. For example, compared to directly generating HDL code using GPT-4-turbo, AutoSilicon enhances the syntax correctness rate by an average of 35.8% and improves functional correctness by an average of 35.6%.
资助项目National Natural Science Foundation of China (NSFC)[62025404] ; National Natural Science Foundation of China (NSFC)[62222411] ; National Key Research and Development Program of China[2023YFB4404400]
WOS研究方向Computer Science
语种英语
WOS记录号WOS:001616616200009
出版者ASSOC COMPUTING MACHINERY
源URL[http://119.78.100.204/handle/2XEOYT63/42961]  
专题中国科学院计算技术研究所
通讯作者Wang, Yujie; Han, Yinhe; Wang, Ying
作者单位1.Peng Cheng Lab, Shenzhen, Peoples R China
2.Chinese Acad Sci, Inst Comp Technol, Res Ctr Intelligent Comp Syst, Beijing, Peoples R China
3.Univ Chinese Acad Sci, Beijing, Peoples R China
4.Univ Chinese Acad Sci, Hangzhou Inst Adv Study, Hangzhou, Peoples R China
5.Chinese Acad Sci, Inst Comp Technol, Beijing, Peoples R China
6.Chinese Acad Sci, Inst Comp Technol, SKLP, Beijing, Peoples R China
7.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processor, Beijing, Peoples R China
8.Zhejiang Lab, Hangzhou, Peoples R China
推荐引用方式
GB/T 7714		 Li, Cangyuan,Chen, Chujie,Pan, Yudong,et al. AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models[J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,2025,30(6):21.
APA Li, Cangyuan.,Chen, Chujie.,Pan, Yudong.,Xu, Wenjun.,Liu, Yiqi.,...&Wang, Ying.(2025).AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,30(6),21.
MLA Li, Cangyuan,et al."AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models".ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 30.6(2025):21.

入库方式： OAI收割

来源：计算技术研究所

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