Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks
文献类型：期刊论文
| 作者 | Wang, Xinrui1; Feng, Lang2; Wang, Yujie3; Xu, Taotao3; Han, Yinhe3; Wang, Zhongfeng1,2 |
| 刊名 | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
 |
| 出版日期 | 2025-09-01 |
| 卷号 | 30期号:5页码:23 |
| 关键词 | Chiplet interposer timing side-channel attack mitigate |
| ISSN号 | 1084-4309 |
| DOI | 10.1145/3748258 |
| 英文摘要 | Chiplet technology has been a hot topic due to its potential for more efficient implementation of large-scale integrated circuits. In chiplet manufacturing, the general-purpose active interposer usually integrates chiplets from different vendors with a typical mesh network. This method of manufacturing is broadly recognized for its cost-efficiency. However, untrusted vendors make the chiplet system vulnerable to security threats such as timing side-channel attacks (TSA) based on network contention information. Even worse, the reliability of each chiplet is usually unknown beforehand to a general-purpose interposer's manufacturer, so that TSAs can be on arbitrary chiplets at arbitrary time in the manufacturer's view. To address this challenge, this work first quantitatively analyzes the attack patterns including reinforced styles, based on which, a resilient interposer architecture named Resister is proposed. A hardware defender is designed in every router to globally detect the malicious transaction patterns at runtime, and adaptively detour the transaction packets accordingly for security while maintaining the performance. According to the evaluation of GEM5 on SPEC 2017 and PARSEC benchmarks, Resister can effectively mitigate TSA with only a 1.7% performance overhead. |
| 资助项目 | National Natural Science Foundation of China[62025404] ; National Natural Science Foundation of China[92473207] ; National Natural Science Foundation of China[62204111] |
| WOS研究方向 | Computer Science |
| 语种 | 英语 |
| WOS记录号 | WOS:001606465600006 |
| 出版者 | ASSOC COMPUTING MACHINERY |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/43103]  |
| 专题 | 中国科学院计算技术研究所 |
| 通讯作者 | Feng, Lang; Wang, Yujie |
| 作者单位 | 1.Nanjing Univ, Nanjing, Peoples R China 2.Sun Yat Sen Univ, Sch Integrated Circuits, Shenzhen, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, Beijing, Peoples R China |
| 推荐引用方式 GB/T 7714 | Wang, Xinrui,Feng, Lang,Wang, Yujie,et al. Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks[J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,2025,30(5):23. |
| APA | Wang, Xinrui,Feng, Lang,Wang, Yujie,Xu, Taotao,Han, Yinhe,&Wang, Zhongfeng.(2025).Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,30(5),23. |
| MLA | Wang, Xinrui,et al."Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks".ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 30.5(2025):23. |
入库方式： OAI收割
来源：计算技术研究所
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