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Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation

文献类型：期刊论文

作者Chao, Zhiteng1,2; Gu, Feng1,2; Huang, Junying1,2; Li, Wenjie1; Ye, Jing1,2,3; Li, Huawei1,2,3; Li, Xiaowei1,2,3
刊名ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
出版日期2025-09-01
卷号30期号:5页码:27
关键词Heterogeneous memory-efficient adaptive
ISSN号1084-4309
DOI10.1145/3760777
英文摘要Gate-level fault simulation is essential for automatic test pattern generation (ATPG). The traditional event-driven simulation is time-consuming due to the large number of faults. While parallel fault simulation with GPGPUs shows promise, it faces reduced parallel efficiency on large circuits. This is mainly due to the increased space required to store fault values, limiting the number of faults that can be processed in parallel and preventing full utilization of the GPU's capabilities. In this study, we propose a memory-efficient fault machine implementation FMgpu based on a circular vector, which is tailored for GPU fault simulation with some sacrifices of time efficiency and a variable length limit. We also propose a fully adaptive parallel fault simulation framework based on the CPU-GPU heterogeneous system, which includes two stages on the GPU and performs CPU simulation at the same time. All parameters related to GPU memory optimization and workload balancing in the framework can be adjusted adaptively. The experimental results demonstrate that our method achieves better memory efficiency and speedup compared to the previous GPU fault simulation methods, a maximum speedup of 137.48x compared to the baseline open-source simulator with 32 threads, and a maximum speedup of 2.52x compared to a 32-thread commercial tool.
资助项目National Natural Science Foundation of China (NSFC)[92373206] ; National Natural Science Foundation of China (NSFC)[92473203] ; Youth Innovation Promotion Association, CAS
WOS研究方向Computer Science
语种英语
WOS记录号WOS:001606095500009
出版者ASSOC COMPUTING MACHINERY
源URL[http://119.78.100.204/handle/2XEOYT63/41606]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Li, Wenjie; Li, Huawei
作者单位1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing, Peoples R China
2.Univ Chinese Acad Sci, Sch Comp Sci & Technol, Beijing, Peoples R China
3.CASTEST Co Ltd, Beijing, Peoples R China
推荐引用方式
GB/T 7714		 Chao, Zhiteng,Gu, Feng,Huang, Junying,et al. Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation[J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,2025,30(5):27.
APA Chao, Zhiteng.,Gu, Feng.,Huang, Junying.,Li, Wenjie.,Ye, Jing.,...&Li, Xiaowei.(2025).Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,30(5),27.
MLA Chao, Zhiteng,et al."Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation".ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 30.5(2025):27.

入库方式： OAI收割

来源：计算技术研究所

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