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GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine

文献类型：期刊论文

作者Fan, Haishuang1,2; Meng, Rui1,2; Sun, Qichu1,2; Wu, Jingya1; Lu, Wenyan1,3; Li, Xiaowei1,2; Yan, Guihai1,3
刊名IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
出版日期2025-10-01
卷号44期号:10页码:3816-3829
关键词Field programmable gate arrays Redundancy Indexes Graphics processing units Central Processing Unit Integrated circuit modeling Computational modeling Engines Design automation Data models Accelerator FPGA Graph processing
ISSN号0278-0070
DOI10.1109/TCAD.2025.3555192
英文摘要Graphs play an important role in various applications. With the rapid expansion of vertices in real life, existing large-scale graph processing frameworks on CPUs and GPUs encounter challenges in optimizing cache usage due to irregular memory access patterns. To address this, graph reordering has been proposed to improve the locality of the graph, but introduces significant overhead without delivering substantial end-to-end performance improvement. While there have been many FPGA-based accelerators for graph processing, achieving high throughput often requires complex graph prepossessing on CPUs. Therefore, implementing an efficient end-to-end graph processing system remains challenging. This article introduces GRACE, an end-to-end FPGA-based graph processing accelerator with a graph reordering engine and a pull-based vertex-centric programming model (PL-VCPM) Engine. First, GRACE employs a customized high-degree vertex cache (HDC) to improve memory access efficiency. Second, GRACE offloads the graph preprocessing to FPGA. We customize an efficient graph reordering engine to complete preprocessing. Third, GRACE adopts a graph pruning strategy to remove the activation and computation redundancy in graph processing. Finally, GRACE introduces a graph conflict board (GCB) to resolve data conflicts and a multiport cache to enhance parallel efficiency. Experimental results demonstrate that GRACE achieves 7.1 x end-to-end performance speedup over CPU and 1.8 x over GPU, as well as 27.3 x and 8.7 x energy efficiency over CPU and GPU. Moreover, GRACE delivers up to 34.9 x performance speedup compared to the state-of-the-art FPGA accelerator.
资助项目National Natural Science Foundation of China (NSFC)[62090020] ; National Natural Science Foundation of China (NSFC)[92373206] ; Strategic Priority Research Program of the Chinese Academy of Sciences[XDB44030100] ; Strategic Priority Research Program of the Chinese Academy of Sciences[XDB0660100] ; Internship Program of YUSUR Technology Company Ltd.
WOS研究方向Computer Science ; Engineering
语种英语
WOS记录号WOS:001577057000019
出版者IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
源URL[http://119.78.100.204/handle/2XEOYT63/41694]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Yan, Guihai
作者单位1.Chinese Acad Sci, Inst Comp Technol, SKLP, Beijing 100190, Peoples R China
2.Univ Chinese Acad Sci, Sch Comp Sci & Technol, Beijing 101408, Peoples R China
3.YUSUR Technol Co Ltd, Beijing 100094, Peoples R China
推荐引用方式
GB/T 7714		 Fan, Haishuang,Meng, Rui,Sun, Qichu,et al. GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2025,44(10):3816-3829.
APA Fan, Haishuang.,Meng, Rui.,Sun, Qichu.,Wu, Jingya.,Lu, Wenyan.,...&Yan, Guihai.(2025).GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,44(10),3816-3829.
MLA Fan, Haishuang,et al."GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 44.10(2025):3816-3829.

入库方式： OAI收割

来源：计算技术研究所

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