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Chinese Academy of Sciences Institutional Repositories Grid
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CAS IR Grid
机构
长春光学精密机械与物... [2]
武汉物理与数学研究所 [1]
采集方式
OAI收割 [3]
内容类型
会议论文 [2]
期刊论文 [1]
发表日期
2013 [1]
2009 [2]
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High-resolution proton CRAMPS NMR using narrowband analog filters and postponed data acquisition
期刊论文
OAI收割
JOURNAL OF MAGNETIC RESONANCE, 2013, 卷号: 234, 页码: 141-146
作者:
Wang, Liying
;
Zhou, Donghua H.
收藏
  |  
浏览/下载:22/0
  |  
提交时间:2015/06/23
High resolution proton spectra
CRAMPS proton NMR
Magic-angle spinning NMR
Audio filter
Postponed data sampling
Noise reduction
An 8-channel, area-efficient, low-power audio sampling rate converter (EI CONFERENCE)
会议论文
OAI收割
9th International Conference on Electronic Measurement and Instruments, ICEMI 2009, August 16, 2009 - August 19, 2009, Beijing, China
作者:
Liu Y.
;
Liu Y.
;
Liu Y.
;
Wang D.
收藏
  |  
浏览/下载:27/0
  |  
提交时间:2013/03/25
A novel 8-channle
third
area-efficient
next a new Timing Division Multiplexer (TMD) scheme lowers clock working rate to minimum in order to save power
a novel memory addressing scheme reduces 20% data memory at least. Experiments show proposed methods could not only saved hardware resources but also reduce power consumption
low-power audio sampling rate converter is proposed in this paper
so it is very suitable for consumer electronics. 2009 IEEE.
conversion ratio is 2:1 and 4:1. Filter design and implementation are the key points for the converter. First
excluded data and coefficients memories
adopting multiplier-free Arithmetic Unit (AU) and rounding methods allows its realization in a cell area of only 0.038mm 2 in 0.18 m technology
A multi-channel, area-efficient, audio sampling rate interpolator (EI CONFERENCE)
会议论文
OAI收割
2009 8th IEEE International Conference on ASIC, ASICON 2009, October 20, 2009 - October 23, 2009, Changsha, China
作者:
Wang D.
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浏览/下载:26/0
  |  
提交时间:2013/03/25
The area and power consumption of sampled rate converter are governed largely by associated digital interpolationfilters. This paper presents a novel multi-channel
area-efficient audio sampling rate interpolator
whose conversion ratio is 1:2 and 1:4. Several architectural and implementation features reduces the complexity of the filter and allow its realization in a die area of 0.032mm2 in 0.18 m technology
meanwhile timing multiplexer scheme reduces clock frequency to minimum. Experiments show proposed methods could not only saved hardware resources but also reduce power consumption
so it is very suitable for consumer electronics. 2009 IEEE.