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	Design of thermostat system based on Proteus simulation software (EI CONFERENCE) 会议论文 OAI收割 2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, August 12, 2011 - August 14, 2011, Harbin, China Han Z.; Song K. 收藏 \| 浏览/下载：39/0 \| 提交时间：2013/03/25 In order to solve the problem of precise temperature control the thermoelectric cooler (TEC) principle widely used is analyzed for the design of the whole control process and selection of control parameters and then accurate simulation model of the TEC is established in Proteus simulation software. Moreover combined with the traditional circuit simulation model the temperature control loop is designed and the response characteristics of the system are tested using an input signal similar to the unit-step function to achieve the precise temperature control. Simulation results show that the proposed control circuits can precisely convert error signal to output voltage sent to TEC model and TEC model behaves approximately like a two-pole system. The first pole starts at 20mHz and a second pole at 1Hz. 2011 IEEE.
	Timing generator of scientific grade CCD camera and its implementation based on FPGA technology (EI CONFERENCE) 会议论文 OAI收割 5th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optoelectronic Materials and Devices for Detector, Imager, Display, and Energy Conversion Technology, April 26, 2010 - April 29, 2010, Dalian, China 作者: Li Y.; Li Y.; Li Y.; Li Y. 收藏 \| 浏览/下载：31/0 \| 提交时间：2013/03/25 The Timing Generator's functions of Scientific Grade CCD Camera is briefly presented: it generates various kinds of impulse sequence for the TDI-CCD video processor and imaging data output acting as the synchronous coordinator for time in the CCD imaging unit. The IL-E2TDI-CCD sensor produced by DALSA Co.Ltd. use in the Scientific Grade CCD Camera. Driving schedules of IL-E2 TDI-CCD sensor has been examined in detail the timing generator has been designed for Scientific Grade CCD Camera. FPGA is chosen as the hardware design platform schedule generator is described with VHDL. The designed generator has been successfully fulfilled function simulation with EDA software and fitted into XC2VP20-FF1152 (a kind of FPGA products made by XILINX). The experiments indicate that the new method improves the integrated level of the system. The Scientific Grade CCD camera system's high reliability stability and low power supply are achieved. At the same time the period of design and experiment is sharply shorted. 2010 Copyright SPIE - The International Society for Optical Engineering.
	高性能低功耗的数字信号处理部件结构设计研究学位论文 OAI收割工学博士, 中国科学院自动化研究所: 中国科学院研究生院, 2008 作者: 李振伟收藏 \| 浏览/下载：48/0 \| 提交时间：2015/09/02 媒体处理器低功耗功能单元结构设计深亚微米 Media Processor Low Power Function Unit Design DSM
	Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China 作者: Sun H.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：30/0 \| 提交时间：2013/03/25 CCD noises and their causes are analyzed. Methods to control these noises such as Correlated Double Sampling (CDS) filtering cooling clamping and calibration are proposed. To improve CCD sensor's performances the IC called Analog Front End (AFE) integration of CDS clamping Programmable Gain Amplifier (PGA) offset and ADC which can fulfill the CDS and analog-to-digital conversion is employed to process the output signal of CCD. Based on the noise control approaches the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator for both CCD and AFE and (2) interface helping to analysis and transfer control command and status information between MCU controller and drive pulse generator or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed such as clock generator for CCD and AFE MCU interface AFE serial interface output interface CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip Xilinx XC2C256-6-VQ100 with 20MHz pixel frequency and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last the design result is presented.