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	An Improvement on the Keypoint Detection Method of SIFT for Hardware Computation 会议论文 OAI收割 Taipei, Taiwan, June 21-25, 2011 作者: Xiao H(肖晗); Yuan K(原魁); He WH(何文浩); Xiao H(肖晗) \| 收藏 \| 浏览/下载：21/0 \| 提交时间：2016/10/17 Sift Hardware Computation Fpga Keypoint Detection
	The parallel computation in one-way hash function designing (EI CONFERENCE) 会议论文 OAI收割 2010 International Conference on Computer, Mechatronics, Control and Electronic Engineering, CMCE 2010, August 24, 2010 - August 26, 2010, Changchun, China 作者: Yang H. 收藏 \| 浏览/下载：17/0 \| 提交时间：2013/03/25 In order to put the parallel one-way hash function into engineering two designing models based on pipeline technology are proposed in this paper. The definition of one-way hash function is shown first and the structure and limitation of the current hash functions are discussed afterward. By analyzing the difference between parallel computation on different platforms and classifying one-way hash functions on application basis the possibility and method of parallel one-way hash function designing on different hardware platforms are described two designing models are constructed for the parallel one-way hash function designing. Finally some attentions for designing are proposed from the engineering angle. The pipeline models that proposed in this paper contact the theoretical rationality and the engineering application of parallel one-way hash function together which can improve the practicality of parallel one-way hash function to a great extent. 2010 IEEE.
	The application of TMS320c64x DSP assembly language in correlation tracking algorithms (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Congress on Image and Signal Processing, CISP 2010, October 16, 2010 - October 18, 2010, Yantai, China Huang D.; Wu Z.; Liang M.; Dong Y.; Peng T. 收藏 \| 浏览/下载：20/0 \| 提交时间：2013/03/25 In order to improve the real-time performance of the conventional correlation tracking algorithm based on full search method for its huge computation amount and vast correlation matching times in the process of searching an optimal matching position a method of combining the TMS320C64x DSP assembly language and software pipelining is proposed to realize template matching which costs the most time of the algorithm. Choose high performance DSP chip TMS320DM642 as the core processor of the hardware platform and schedule each one of the instruction in the algorithm to maximize performance using the instruction-level parallelism of the DSP. The experimental results indicate the time of template image matching implemented in assembly language has decreased from 49.36ms to 0.62ms. It is concluded that the correlation tracking adopting proposed method can meet the real-time and stability requirement of the target tracking. 2010 IEEE.
	A design of high-speed and low-consume parallel grouping RS code and simulation (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China Chen C.; Jin G. 收藏 \| 浏览/下载：25/0 \| 提交时间：2013/03/25 RS code is a linear error correction codes with better error correction capability is widely used in different kinds of occasions for communications or data storage. But for its high difficulty of coding and decoding algorithm and low throughput optimization RS algorithm is always studied as one of the focus in the error-correction field. A new coding method parallel coding and decoding data into groups in lower step finite field for avoiding complex matrix iteration and Chien search computation is proposed in this paper. It is proved that the coding and decoding throughput of the parallel grouping RS coder is increased and the hardware complexity is reduced with changeless error-correction capability from the simulation results using ModelSim SE 6.0 and synthetic results using ISE 9.11. 2010 IEEE.