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	A High-Parallelism Detection Algorithm for Massive MIMO Systems 会议论文 OAI收割中国深圳, 2017.07.23-2017.07.26 作者: Li H; Zhao X; Guo C; Wang D \| 收藏 \| 浏览/下载：17/0 \| 提交时间：2018/06/01 Massive Mimo Signal Detection High Parallelism Matrix Blocking
	The application of TMS320c64x DSP assembly language in correlation tracking algorithms (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Congress on Image and Signal Processing, CISP 2010, October 16, 2010 - October 18, 2010, Yantai, China Huang D.; Wu Z.; Liang M.; Dong Y.; Peng T. 收藏 \| 浏览/下载：20/0 \| 提交时间：2013/03/25 In order to improve the real-time performance of the conventional correlation tracking algorithm based on full search method for its huge computation amount and vast correlation matching times in the process of searching an optimal matching position a method of combining the TMS320C64x DSP assembly language and software pipelining is proposed to realize template matching which costs the most time of the algorithm. Choose high performance DSP chip TMS320DM642 as the core processor of the hardware platform and schedule each one of the instruction in the algorithm to maximize performance using the instruction-level parallelism of the DSP. The experimental results indicate the time of template image matching implemented in assembly language has decreased from 49.36ms to 0.62ms. It is concluded that the correlation tracking adopting proposed method can meet the real-time and stability requirement of the target tracking. 2010 IEEE.
	High performance general-purpose microprocessors: Past and future 期刊论文 OAI收割 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2006, 卷号: 21, 期号: 5, 页码: 631-640 作者: Hu, Wei-Wu; Hou, Rui; Xiao, Jun-Hua; Zhang, Long-Bin \| 收藏 \| 浏览/下载：20/0 \| 提交时间：2019/12/16 high performance general-purpose microprocessor instruction level parallelism data level parallelism thread level parallelism chip multiprocessors Godson processor
	Design and DSP implementation of star image acquisition and Star point fast acquiring tracking (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 2, 2005 - November 5, 2005, Zian, China 作者: Wang X.; Wang X.; Wang X. 收藏 \| 浏览/下载：22/0 \| 提交时间：2013/03/25 Star sensor is a special high accuracy photoelectric sensor. Attitude acquisition time is an important function index of star sensor. In this paper the design target is to acquire 10 samples per second dynamic performance. On the basis of analyzing CCD signals timing and star image processing a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design the operation moving the data in expanded windows including the star to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. During the CCD saving the star image to memory DSP processes the data in the on-chip memory. This parallelism greatly improves the efficiency of processing. The scheme proposed here results in enormous savings of memory normally required. In the scheme DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The efficiency of processing is discussed in numerical tests. Only in 3.5ms is acquired the five lightest stars in the star acquisition stage. In 43us the data in five expanded windows including stars are moved into the internal memory of DSP and in 1.6ms five star coordinates are achieved in the star tracking stage.