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长春光学精密机械与物... [3]
计算技术研究所 [2]
数学与系统科学研究院 [1]
软件研究所 [1]
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OAI收割 [7]
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会议论文 [4]
期刊论文 [3]
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2024 [1]
2022 [1]
2021 [1]
2009 [2]
2006 [2]
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Efficient Quantum Circuit Synthesis for SAT-Oracle With Limited Ancillary Qubit
期刊论文
OAI收割
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 3, 页码: 868-877
作者:
Yang, Shuai
;
Zi, Wei
;
Wu, Bujiao
;
Guo, Cheng
;
Zhang, Jialin
  |  
收藏
  |  
浏览/下载:27/0
  |  
提交时间:2024/12/06
Qubit
Logic gates
Boolean functions
Quantum circuit
Quantum algorithm
Circuit synthesis
Sun
limited ancillary qubit
satisfiability (SAT) problem
SAT-oracle
space-depth tradeoff
Observability Criteria for Boolean Networks
期刊论文
OAI收割
IEEE TRANSACTIONS ON AUTOMATIC CONTROL, 2022, 卷号: 67, 期号: 11, 页码: 6248-6254
作者:
Yu, Yongyuan
;
Meng, Min
;
Feng, Jun-E
;
Chen, Ge
  |  
收藏
  |  
浏览/下载:44/0
  |  
提交时间:2023/02/07
Observability
Symmetric matrices
Probabilistic logic
Germanium
Boolean functions
Aerospace electronics
Upper bound
Boolean control network (BCN)
nonaugmented method
observability
probabilistic Boolean network (PBN)
Integrating Two Logics Into One Crossbar Array for Logic Gate Design
期刊论文
OAI收割
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 卷号: 68, 期号: 8, 页码: 2987-2991
作者:
Yao, Lian
;
Liu, Peng
;
Wu, Jigang
;
Han, Yinhe
;
Zhong, Yuehang
  |  
收藏
  |  
浏览/下载:68/0
  |  
提交时间:2021/12/01
Logic gates
Memristors
Logic arrays
Resistance
Logic functions
Adders
Switches
Logic gates
memristive crossbar
material implication
not material implication
1-bit full adder
Intelligent traffic control system based on DSP and Nios II (EI CONFERENCE)
会议论文
OAI收割
2009 International Asia Conference on Informatics in Control, Automation, and Robotics, CAR 2009, February 1, 2009 - September 2, 2009, Bangkok, Thailand
作者:
Liu W.
;
Zheng X.
收藏
  |  
浏览/下载:39/0
  |  
提交时间:2013/03/25
In view of domestic traffic
the traffic flow is increasing rapidly recent years
whereas the traffic control is deficient. This paper presents a design of intelligent traffic control system based on DSP and Nios II. Using Dual-CPU
Intelligent Traffic Control System combined with logic control in FPGA implements kinds of functions
which include crossphase adjustment
exchanging and establishing related information
live human-computer interaction and remote control etc. The system works mostly at the mode of timing and multiple phases according to the user demands dynamically
thus it breaks through the bottleneck of traditional traffic signal controller
and can accomplish the control in complicated and diversified traffic. This paper gives the realization of hardware system as well as the software system. The experiment results show that the Intelligent Traffic Control System can completely meet the requirements of modern traffic control. 2009 IEEE.
volume computation for boolean combination of linear arithmetic constraints
会议论文
OAI收割
22nd International Conference on Automated Deduction (CADE-22), Montreal, CANADA, AUG 02-07,
Ma Feifei
;
Liu Sheng
;
Zhang Jian
  |  
收藏
  |  
浏览/下载:50/0
  |  
提交时间:2011/03/20
Automation
Boolean functions
Formal logic
Learning algorithms
Topology
Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE)
会议论文
OAI收割
2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China
作者:
Sun H.
;
Wang Y.
;
Wang Y.
;
Wang Y.
;
Wang Y.
收藏
  |  
浏览/下载:49/0
  |  
提交时间:2013/03/25
CCD noises and their causes are analyzed. Methods to control these noises
such as Correlated Double Sampling (CDS)
filtering
cooling
clamping
and calibration are proposed. To improve CCD sensor's performances
the IC
called Analog Front End (AFE)
integration of CDS
clamping
Programmable Gain Amplifier (PGA)
offset
and ADC
which can fulfill the CDS and analog-to-digital conversion
is employed to process the output signal of CCD. Based on the noise control approaches
the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator
for both CCD and AFE
and (2) interface
helping to analysis and transfer control command and status information between MCU controller and drive pulse generator
or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed
such as clock generator for CCD and AFE
MCU interface
AFE serial interface
output interface
CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip
Xilinx XC2C256-6-VQ100
with 20MHz pixel frequency
and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last
the design result is presented.
An image identification system of seal with fingerprint based on CMOS image sensor (EI CONFERENCE)
会议论文
OAI收割
ICO20: Optical Information Processing, August 21, 2005 - August 26, 2005, Changchun, China
作者:
Xue X.-C.
收藏
  |  
浏览/下载:34/0
  |  
提交时间:2013/03/25
CMOS image sensors now become increasingly competitive with respect to their CCD counterparts
while adding advantages such as no blooming
simpler driving requirements and the potential of on-chip integration of sensor
analog signal conditioning circuits
A/D converter and digital processing functions. Furthermore
CMOS sensors are the best choices for low-cost imaging systems. An image identification system based on CMOS image sensor is used to identify the seal images that include fingerprint
and then determine whether the seal is fake or not. The system consists of a color CMOS image sensor (OV2610)
a buffer memory
a CPLD
a MCU (P89C61X2)
a USB2.0 interface chip (ISP1581) and a personal computer. The CPLD implement the logic and timing of the system. The MCU and the USB2.0 interface chip deal with the communications between the images acquisition system and PC. Thus PC can send some parameters and commands to the images acquisition system and also read image data from it. The identification of the images of seal is processed by the PC. The structure and scheme of the system are discussed in detail in this paper. Several test images of seal taken by the system are also provided in the paper.