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浏览/检索结果: 共11条,第1-10条 帮助

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GNSS Timing Performance Assessment and Results Analysis 期刊论文  OAI收割
SENSORS, 2022, 卷号: 22, 期号: 7, 页码: 10
作者:  
Zhu, Lin;  Zhang, Huijun;  Li, Xiaohui;  Zhu, Feng;  Liu, Yinhua
  |  收藏  |  浏览/下载:40/0  |  提交时间:2022/08/15
Effects of secondary electron emission yield properties on gain and timing performance of ALD-coated MCP 期刊论文  OAI收割
Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2021, 卷号: 1005
作者:  
Guo, Lehui;  Xin, Liwei;  Li, Lili;  Gou, Yongsheng;  Sai, Xiaofeng
  |  收藏  |  浏览/下载:58/0  |  提交时间:2021/05/24
Feed-forward timing estimation for burst signals in non-cooperative communication 期刊论文  OAI收割
IET COMMUNICATIONS, 2020, 卷号: 14, 期号: 17, 页码: 2871-2877
作者:  
Li, Youyang;  Qin, Fei;  Wang, Xue;  Lu, Xiaochun;  Chu, Ziyue
  |  收藏  |  浏览/下载:45/0  |  提交时间:2021/11/29
Timing performance evaluation of Radio Determination Satellite Service (RDSS) for Beidou system 期刊论文  OAI收割
ACTA ASTRONAUTICA, 2019, 卷号: 156, 页码: 125-133
作者:  
Wang, Dongxia;  Guo, Rui;  Zhang, Tianqiao;  Hu, Xiaogong
  |  收藏  |  浏览/下载:51/0  |  提交时间:2019/05/23
Longitudinal Jitter Analysis of a Linear Accelerator Electron Gun 期刊论文  OAI收割
Applied Sciences-Basel, 2016, 卷号: 6, 期号: 11
作者:  
Liu MS(刘明善);  Iqbal, M;  Liu, M
  |  收藏  |  浏览/下载:35/0  |  提交时间:2017/07/25
Design of high speed and parallel compression system used in the big area CCD of high frame frequency (EI CONFERENCE) 会议论文  OAI收割
2011 International Conference on Precision Engineering and Non-Traditional Machining, PENTM 2011, December 9, 2011 - December 11, 2011, Xi'an, China
作者:  
Li G.-N.;  Jin L.-X.;  Zhang R.-F.;  Wang W.-H.;  Li G.-N.
收藏  |  浏览/下载:53/0  |  提交时间:2013/03/25
According to the area CCD camera of characteristics  such as high resolution capacity and high frame frequency  this paper puts forward a high speed and parallel image compression system of high integration degree. Firstly  according to the work principle of the area CCD  FPGA is adopted to realize the timing driving and multichannel and parallel analog signal handling to raise the export frame frequency of the area CCD. Secondly  with an image compression scheme based on FPGA embedded processor MicroBlaze and ADV212 compression chip  real time image compression and the high speed area CCD are realized. Finally  by detecting the analog signal of the area CCD output  the real time compression of the big area CCD image is carried out in different compression ratios and the compression performance is analyzed. Experiment result shows that this scheme can realize real time image compression with the biggest data rate of 520Mbps. When compression bit ratio is 0.15  the signal-to-noise ratio of peak value can reach 36 dB. Image collection and image compression are integrated  which reduces the data transmission between them and improves systematic integration degree.  
MicroFix: Using Timing Interpolation and Delay Sensors for Power Reduction 期刊论文  OAI收割
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2011, 卷号: 16, 期号: 2, 页码: 21
作者:  
Yan, Guihai;  Han, Yinhe;  Liu, Hui;  Liang, Xiaoyao;  Li, Xiaowei
  |  收藏  |  浏览/下载:15/0  |  提交时间:2019/12/16
Design of driving circuit for binocular CCD image system (EI CONFERENCE) 会议论文  OAI收割
5th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optoelectronic Materials and Devices for Detector, Imager, Display, and Energy Conversion Technology, April 26, 2010 - April 29, 2010, Dalian, China
作者:  
Zhang X.;  Zhang X.;  Zhang X.
收藏  |  浏览/下载:43/0  |  提交时间:2013/03/25
The paper designs a driving circuit of high sensitive  wide dynamic and high signal-to-noise ratio for binocular CCD imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Inner structure and driving timing of the FTF5066M sensor are presented. Field Programmable Gate Array (FPGA) is used as the main device to accomplish the timing design of the circuits and power driver control of the two sensors. By using the Correlated Double Sampling (CDS) technique  the video noise is reduced and the SNR of the system is increased. A 12- bit A/D converter is used to improve the image quality. The output rate of the imaging system designed with integrated chip can reach to 1.3 frames per second through bi-channel. For its good performance  low power consumption and small volume  the driving system can be applied to aeronautics and astronautics field. With a further improvement  a maximum data output rate of 2.7 frames per second can be reached through all the eight channels of the two CCDs. 2010 Copyright SPIE - The International Society for Optical Engineering.  
The design of high-speed optical fiber communication system based on PCI bus (EI CONFERENCE) 会议论文  OAI收割
2010 2nd IEEE International Conference on Advanced Management Science, ICAMS 2010, July 9, 2010 - July 11, 2010, Chengdu, China
作者:  
Zhang L.-G.;  Zhang L.-G.;  He X.
收藏  |  浏览/下载:57/0  |  提交时间:2013/03/25
In order to increase the transmission distance and reduce noise effectively  a communication system with the optical fiber interface is developed in this paper. In the system  the PCI bus is adopted as the connection bus between the underlying optical fiber transceiver module circuitry and host computer using the WDM driver. The FPGA is the core logic of the whole system  responsible for data transmission and timing logic control. The module structure and the design method of the PCI bus  the principle and the design of optical interface module and the bottom-driven development are described in this paper. The experiment results show that the system has basically meet requirement targets. It can achieve the maximum transfer rate of 40MBps when running in the DMA mode. With long transmission distance  strong antiinterference and high scalability  this system has stable and reliable performance. 2010 IEEE.  
High speed, low memory image coding using zero blocks of wavelet coefficients (EI CONFERENCE) 会议论文  OAI收割
4th International Conference on Image and Graphics, ICIG 2007, August 22, 2007 - August 24, 2007, Chengdu, China
作者:  
Zhang T.;  Yang W.-G.
收藏  |  浏览/下载:34/0  |  提交时间:2013/03/25
We propose a new high speed  low memory SPECK image coder based on the form of block-unit states  called LBUS-SPECK  which uses the form of block-unit states and the form of block exponents to substitute LIS and LSP of SPECK. A form of block-unit states is introduced to store the significance flag of coefficients and the value of the block-unit exponents. A form of block exponents is introduced to store the block exponents which are used to represent the max coefficient in a decomposed block. A new block depth-finding strategy is developed for searching insignificant sets at sorting stage. Experimental results show that the obtained PSNR values for the decoded images are very close to those of SPECK algorithm and the memory consumption is reduced by 9 times  the encoding timing is saved about 15%. Comparing with SPECK algorithm  this algorithm not only has better performance of the decoded images  but also is easy to implement  especially  it provides an efficient way for hardware implementation of wavelet embedded block coding. 2007 IEEE.