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General Purpose Deep Learning Accelerator Based on Bit Interleaving 期刊论文  OAI收割
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 5, 页码: 1470-1483
作者:  
Chang, Liang;  Lu, Hang;  Li, Chenglong;  Zhao, Xin;  Hu, Zhicheng
  |  收藏  |  浏览/下载:6/0  |  提交时间:2024/12/06
Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator 期刊论文  OAI收割
IEICE ELECTRONICS EXPRESS, 2019, 卷号: 16, 期号: 14, 页码: 6
作者:  
Zhang, Shichang;  Wang, Ying;  Chen, Xiaoming;  Han, Yinhe;  Wang, Yujie
  |  收藏  |  浏览/下载:101/0  |  提交时间:2019/12/10
Communication synchronization in wireless optical link (EI CONFERENCE) 会议论文  OAI收割
2012 International Conference on Control Engineering and Communication Technology, ICCECT 2012, December 7, 2012 - December 9, 2012, Shenyang, Liaoning, China
作者:  
Guo J.;  Guo J.;  Wang H.;  Wang H.;  Wang H.
收藏  |  浏览/下载:31/0  |  提交时间:2013/03/25
An FPGA based transceiving synchronization method is demonstrated for Free Space Optical (FSO) communication system  which is discussed separately as the transmitting protocol and the receiving protocol. During the discussion of these two parts  the co-operation of them is also discussed. The transmitting protocol interfaces the outer input data with a parallel port  buffers the input data  encodes the input data stream  serializes the parallel data and outputs the serialized data. It also has an output management unit to manage the activity of each part of the transmitting protocol. The receiving protocol filters and synchronizes the input serial data stream  parallels the serial data stream  decodes the input data  checks received error  handles transmission exception and interfaces the outer receiver with a parallel port. The entire transceiving protocol could be programmed into a single FPGA chip to improve system integrity and reduce the system cost. The presented protocol could be taken as "protocol transparent" for outer interfaces  meaning that when interfacing the presented system to an outer system  users don't have to consider what protocol the outer system transceiving data stream is under  for example  the TCP/IP protocol or anything else  in the case that its I/O interface is a parallel port. Simulation and final experiment prove that the protocol presented is a working solution at a certain bit rate scale. 2012 IEEE.  
Design of high speed and parallel compression system used in the big area CCD of high frame frequency (EI CONFERENCE) 会议论文  OAI收割
2011 International Conference on Precision Engineering and Non-Traditional Machining, PENTM 2011, December 9, 2011 - December 11, 2011, Xi'an, China
作者:  
Li G.-N.;  Jin L.-X.;  Zhang R.-F.;  Wang W.-H.;  Li G.-N.
收藏  |  浏览/下载:53/0  |  提交时间:2013/03/25
According to the area CCD camera of characteristics  such as high resolution capacity and high frame frequency  this paper puts forward a high speed and parallel image compression system of high integration degree. Firstly  according to the work principle of the area CCD  FPGA is adopted to realize the timing driving and multichannel and parallel analog signal handling to raise the export frame frequency of the area CCD. Secondly  with an image compression scheme based on FPGA embedded processor MicroBlaze and ADV212 compression chip  real time image compression and the high speed area CCD are realized. Finally  by detecting the analog signal of the area CCD output  the real time compression of the big area CCD image is carried out in different compression ratios and the compression performance is analyzed. Experiment result shows that this scheme can realize real time image compression with the biggest data rate of 520Mbps. When compression bit ratio is 0.15  the signal-to-noise ratio of peak value can reach 36 dB. Image collection and image compression are integrated  which reduces the data transmission between them and improves systematic integration degree.  
A small thickness measurement system based on PSD and FPGA (EI CONFERENCE) 会议论文  OAI收割
3rd International Conference on Measuring Technology and Mechatronics Automation, ICMTMA 2011, January 6, 2011 - January 7, 2011, Shanghai, China
作者:  
Guo J.;  Guo J.;  He X.
收藏  |  浏览/下载:30/0  |  提交时间:2013/03/25
Considering that the requirement of industrial manufacture  An AT89S51 singlechip works as the core processor of the system. By two laser triangulation  a small thickness measurement system based on PSD and FPGA is presented. It takes S3931 PSD of one dimension as position detection device  A FPGA produces logic control signals for the whole system  the small displacement is converted to differential voltages  which is made by Hamamatsu in Japan  and after amplification and A/D transformation  8-bit parallel data is send to singlechip from FPGA by external interrupts  and the final calculation results output to the LCD display module. After digital micro meter calibration  we get the small thickness. Experiments show that the detection accuracy of the system is not less than 10um.  
Optical transmission system based on 10GBASE-X (EI CONFERENCE) 会议论文  OAI收割
2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China
作者:  
Gao S.-J.
收藏  |  浏览/下载:31/0  |  提交时间:2013/03/25
In order to further enhance the bandwidth of the data communication system in theodolite  The whole design of the PMD is realized by using Xenpak optical module. Its duty is responsible for converting 4-channel parallel 3.125Gbps data stream into a serial 10.3126Gbps data stream  a single channel serial optical transmission system was designed based on the studying of the 10BASE-X Gigabit Ethernet physical layer technology which meets the IEEE standard. The conversion between the 64-bit 156.25MHz TTL signals and the 4 channel 3.125Gbps PCML differential signals is carried out by FPGA  and sending out it in the form of light signals. The experimental results show that data transmission capacity was achieved a 10Gbps in the single-channel optical transmission system. It can conduct short distance transmission. The system delay is about 31lns. The bit error rates no more than 10-12  which satisfies the system demand. 2010 IEEE.  
An improved fast parallel SPIHT algorithm and its FPGA implementation (EI CONFERENCE) 会议论文  OAI收割
2010 2nd International Conference on Future Computer and Communication, ICFCC 2010, May 21, 2010 - May 24, 2010, Wuhan, China
作者:  
Jin L.-X.;  Tao H.-J.;  Wu Y.-H.
收藏  |  浏览/下载:22/0  |  提交时间:2013/03/25
In view of the current stringent need to the real-time compression algorithm of the high-speed and high-resolution image  such as remote sensing or medical image and so on  in this paper  No List SPIHT (NLS) algorithm has been improved  and a fast parallel SPIHT algorithm is proposed  which is suitable to implement with FPGA. It can deal with all bit-planes simultaneously  and process in the speed of 4pixels/period  so the encoding time is only relative to the image resolution. The experimental results show that  the processing capacity can achieve 200MPixels/s  when the input clock is 50MHz  the system of this paper need 2.29ms to complete lossless compression of a 512x512x8bit image  and only requires 1.31ms in the optimal state. The improved algorithm keeps the high SNR unchanged  increases the speed greatly and reduces the size of the needed storage space. It can implement lossless or lossy compression  and the compression ratio can be controlled. It could be widely used in the field of the high-speed and high-resolution image compression. 2010 IEEE.  
Transceiving protocol designc for a free space optical communication system (EI CONFERENCE) 会议论文  OAI收割
2008 International Conference on Optical Instruments and Technology: Optical Systems and Optoelectronic Instruments, November 16, 2008 - November 19, 2008, Beijing, China
Hualong W.; Wanxin S.; Zhongbao X.
收藏  |  浏览/下载:58/0  |  提交时间:2013/03/25
A new transceiving protocol is demonstrated for a Free Space Optical (FSO) communication system  and it's discussed in two parts: the transmitting protocol and the receiving protocol. During the discussion of these two parts  the cooperation of them is also discussed. Different from wired communication  an FSO system modulates the data on a narrow beam of laser transmitting through the free space or the atmosphere  and the protocol presented in this paper is mainly optimized for terrestrial Free Space Optical links  in which the signal channel of the system is mainly the atmosphere. Due to the complex composition and activity of the atmosphere  this signal channel brings in great influence on the transmitting laser in it  for example  the absorption and scattering of the atmosphere molecules and aerosols  the scintillation of received laser power caused by the turbulence of the atmosphere  all of which results in a much higher Bit Error Rate (BER) of the communication system. Thus in designing a protocol for an FSO system  more effort should be taken in the encoding of the data stream  the synchronization of the data stream  error checking and exception handling. The main function of the transmitting protocol includes interfacing the outer input data with a parallel port  buffering the input data  encoding the input data stream  serializing the parallel data and output the serialized data. It also has an output management unit to manage the activity of each part of the transmitting protocol. The main function of the receiving protocol includes filtering and synchronizing the input serial data stream  paralleling the serial data stream  decoding the input data  error checking  exception handling and interfacing the outer receiver with a parallel port. The entire transceiving protocol could be programmed into a single FPGA chip to improve system integrity and reduce the system cost. The presented protocol could be taken as "protocol transparent" for outer interfaces  meaning that when interfacing the presented system to an outer system  you don't have to consider what protocol the outer system transceiving data stream is under  for example  the TCP/IP protocol or anything else  in the case that its I/O interface is a parallel port. Simulation and final experiment prove that the protocol presented is working fine at a certain bit rate scale. 2009 SPIE.  
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