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	Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator 期刊论文 OAI收割 IEICE ELECTRONICS EXPRESS, 2019, 卷号: 16, 期号: 14, 页码: 6 作者: Zhang, Shichang; Wang, Ying; Chen, Xiaoming; Han, Yinhe; Wang, Yujie \| 收藏 \| 浏览/下载：101/0 \| 提交时间：2019/12/10 DNN accelerator variable bit-precision bit-serial bit-parallel fine-grained precision
	Communication synchronization in wireless optical link (EI CONFERENCE) 会议论文 OAI收割 2012 International Conference on Control Engineering and Communication Technology, ICCECT 2012, December 7, 2012 - December 9, 2012, Shenyang, Liaoning, China 作者: Guo J.; Guo J.; Wang H.; Wang H.; Wang H. 收藏 \| 浏览/下载：31/0 \| 提交时间：2013/03/25 An FPGA based transceiving synchronization method is demonstrated for Free Space Optical (FSO) communication system which is discussed separately as the transmitting protocol and the receiving protocol. During the discussion of these two parts the co-operation of them is also discussed. The transmitting protocol interfaces the outer input data with a parallel port buffers the input data encodes the input data stream serializes the parallel data and outputs the serialized data. It also has an output management unit to manage the activity of each part of the transmitting protocol. The receiving protocol filters and synchronizes the input serial data stream parallels the serial data stream decodes the input data checks received error handles transmission exception and interfaces the outer receiver with a parallel port. The entire transceiving protocol could be programmed into a single FPGA chip to improve system integrity and reduce the system cost. The presented protocol could be taken as "protocol transparent" for outer interfaces meaning that when interfacing the presented system to an outer system users don't have to consider what protocol the outer system transceiving data stream is under for example the TCP/IP protocol or anything else in the case that its I/O interface is a parallel port. Simulation and final experiment prove that the protocol presented is a working solution at a certain bit rate scale. 2012 IEEE.
	A new approach to realize UART (EI CONFERENCE) 会议论文 OAI收割 2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, August 12, 2011 - August 14, 2011, Harbin, China 作者: Wang Y.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：36/0 \| 提交时间：2013/03/25 In order to connect DSP which has synchronous serial ports to the devices implementing asynchronous communications protocol a method to implement UART communications based on programmable logic device is proposed in the paper. In the proposed method the core function of UART is integrated in CPLD with VHDL. Firstly UART data frame format and operational principle of UART were introduced after reviewing some methods to realize UART. The methods to implement UART transmitter UART receiver and baudrate generator using VHDL were illustrated in detail. Then pre-simulation and synthesize of VHDL program were executed. Finally the test with bit error rate was carried out on physical system. Experimental results indicate that 75 percent of the GLB are used by UART and the bit error rate is less than 109. The experiment was implemented utilizing the RS-422 protocol and the baudrate is 62.5kb/s. The proposed method can satisfy the system requirements of high integration stabilization low bit error rate strong anti-jamming and low cost. 2011 IEEE.
	Optical transmission system based on 10GBASE-X (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China 作者: Gao S.-J. 收藏 \| 浏览/下载：30/0 \| 提交时间：2013/03/25 In order to further enhance the bandwidth of the data communication system in theodolite The whole design of the PMD is realized by using Xenpak optical module. Its duty is responsible for converting 4-channel parallel 3.125Gbps data stream into a serial 10.3126Gbps data stream a single channel serial optical transmission system was designed based on the studying of the 10BASE-X Gigabit Ethernet physical layer technology which meets the IEEE standard. The conversion between the 64-bit 156.25MHz TTL signals and the 4 channel 3.125Gbps PCML differential signals is carried out by FPGA and sending out it in the form of light signals. The experimental results show that data transmission capacity was achieved a 10Gbps in the single-channel optical transmission system. It can conduct short distance transmission. The system delay is about 31lns. The bit error rates no more than 10-12 which satisfies the system demand. 2010 IEEE.
	Transceiving protocol designc for a free space optical communication system (EI CONFERENCE) 会议论文 OAI收割 2008 International Conference on Optical Instruments and Technology: Optical Systems and Optoelectronic Instruments, November 16, 2008 - November 19, 2008, Beijing, China Hualong W.; Wanxin S.; Zhongbao X. 收藏 \| 浏览/下载：58/0 \| 提交时间：2013/03/25 A new transceiving protocol is demonstrated for a Free Space Optical (FSO) communication system and it's discussed in two parts: the transmitting protocol and the receiving protocol. During the discussion of these two parts the cooperation of them is also discussed. Different from wired communication an FSO system modulates the data on a narrow beam of laser transmitting through the free space or the atmosphere and the protocol presented in this paper is mainly optimized for terrestrial Free Space Optical links in which the signal channel of the system is mainly the atmosphere. Due to the complex composition and activity of the atmosphere this signal channel brings in great influence on the transmitting laser in it for example the absorption and scattering of the atmosphere molecules and aerosols the scintillation of received laser power caused by the turbulence of the atmosphere all of which results in a much higher Bit Error Rate (BER) of the communication system. Thus in designing a protocol for an FSO system more effort should be taken in the encoding of the data stream the synchronization of the data stream error checking and exception handling. The main function of the transmitting protocol includes interfacing the outer input data with a parallel port buffering the input data encoding the input data stream serializing the parallel data and output the serialized data. It also has an output management unit to manage the activity of each part of the transmitting protocol. The main function of the receiving protocol includes filtering and synchronizing the input serial data stream paralleling the serial data stream decoding the input data error checking exception handling and interfacing the outer receiver with a parallel port. The entire transceiving protocol could be programmed into a single FPGA chip to improve system integrity and reduce the system cost. The presented protocol could be taken as "protocol transparent" for outer interfaces meaning that when interfacing the presented system to an outer system you don't have to consider what protocol the outer system transceiving data stream is under for example the TCP/IP protocol or anything else in the case that its I/O interface is a parallel port. Simulation and final experiment prove that the protocol presented is working fine at a certain bit rate scale. 2009 SPIE.
	Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China 作者: Sun H.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：31/0 \| 提交时间：2013/03/25 CCD noises and their causes are analyzed. Methods to control these noises such as Correlated Double Sampling (CDS) filtering cooling clamping and calibration are proposed. To improve CCD sensor's performances the IC called Analog Front End (AFE) integration of CDS clamping Programmable Gain Amplifier (PGA) offset and ADC which can fulfill the CDS and analog-to-digital conversion is employed to process the output signal of CCD. Based on the noise control approaches the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator for both CCD and AFE and (2) interface helping to analysis and transfer control command and status information between MCU controller and drive pulse generator or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed such as clock generator for CCD and AFE MCU interface AFE serial interface output interface CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip Xilinx XC2C256-6-VQ100 with 20MHz pixel frequency and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last the design result is presented.