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	Optimus: An Operator Fusion Framework for Deep Neural Networks 期刊论文 OAI收割 ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2023, 卷号: 22, 期号: 1, 页码: 26 作者: Cai, Xuyi; Wang, Ying; Zhang, Lei \| 收藏 \| 浏览/下载：17/0 \| 提交时间：2023/07/12 Neural network embedded processor memory layer fusion
	Design of high speed and parallel compression system used in the big area CCD of high frame frequency (EI CONFERENCE) 会议论文 OAI收割 2011 International Conference on Precision Engineering and Non-Traditional Machining, PENTM 2011, December 9, 2011 - December 11, 2011, Xi'an, China 作者: Li G.-N.; Jin L.-X.; Zhang R.-F.; Wang W.-H.; Li G.-N. 收藏 \| 浏览/下载：55/0 \| 提交时间：2013/03/25 According to the area CCD camera of characteristics such as high resolution capacity and high frame frequency this paper puts forward a high speed and parallel image compression system of high integration degree. Firstly according to the work principle of the area CCD FPGA is adopted to realize the timing driving and multichannel and parallel analog signal handling to raise the export frame frequency of the area CCD. Secondly with an image compression scheme based on FPGA embedded processor MicroBlaze and ADV212 compression chip real time image compression and the high speed area CCD are realized. Finally by detecting the analog signal of the area CCD output the real time compression of the big area CCD image is carried out in different compression ratios and the compression performance is analyzed. Experiment result shows that this scheme can realize real time image compression with the biggest data rate of 520Mbps. When compression bit ratio is 0.15 the signal-to-noise ratio of peak value can reach 36 dB. Image collection and image compression are integrated which reduces the data transmission between them and improves systematic integration degree.
	基于ARM的嵌入式视觉定位系统学位论文 OAI收割工学硕士, 中国科学院自动化研究所: 中国科学院研究生院, 2010 作者: 邹伟收藏 \| 浏览/下载：39/0 \| 提交时间：2015/09/02 嵌入式视觉 ARM处理器自适应阈值图像处理特征提取 RANSAC PnP定位视觉定位 Embedded vision ARM processor adaptive threshold image processing feature extraction RANSAC PnP-based positioning visual positioning
	Bootstrap loader design of aerospace payload controller based on TSC695F (EI CONFERENCE) 会议论文 OAI收割 2010 2nd International Conference on Computational Intelligence and Natural Computing, CINC 2010, September 13, 2010 - September 14, 2010, Wuhan, China Xu W.; Piao Y. 收藏 \| 浏览/下载：39/0 \| 提交时间：2013/03/25 Anti-radiation TSC695F is usually used as aerospace payload controller in tasks to ensure the aerospace payload having extremely high reliability in abominable space environment. The processor bases on SP ARC V7 architecture with parity check and EDAC so it could design out high reliable bootstrap loader to guarantee the operation system of VxWorks and application codes loaded correctly and worked stable and high effective. First this paper put forward the system hardware composition and boot mode which apply for aerospace payload then it makes clear the related contents of register group initialization stack initialization system hardware initialization in bootstrap loader of TSC695F and give out the method to establish TRAP table. That's all through comparing different type of organize mode of program image. After that compiling of target codes have been described and the kernel code of MakeFile had been given at the same time for reference aimed at the realization of engineering. Although this paper is based on TSC695F but it could be extended to other embedded system based on SP ARC for bootstrap loader analysis and design for example the TSC697 which based on SP ARC V8 with higher performance so this paper has extremely high engineering value. 2010 IEEE.
	Design of image interpretation and data-processing system based on SOPC (EI CONFERENCE) 会议论文 OAI收割 2010 International Conference on Computer, Mechatronics, Control and Electronic Engineering, CMCE 2010, August 24, 2010 - August 26, 2010, Changchun, China Wang Z.-Q.; Liu Z.-R.; Xie M.-J. 收藏 \| 浏览/下载：30/0 \| 提交时间：2013/03/25 In order to follow the development of image interpretation and data-processing system in photoelectric measurement equipments a kind of hardware acceleration system is designed where MIMD distributed multi-processor architecture is used with SOPC technology. System hardware is composed of FPGA SDRAM SRAM FLASH and PCI bridge chip. Four Nios II embedded processors are integrated in a single FPGA chip and communicate with each other by sharing memory. Experimental results indicate that the system meets the requirements of data-processing system in photoelectric measurement equipments and possesses practical significance for engineering applications. 2010 IEEE.
	Real-time video compressing under DSP/BIOS (EI CONFERENCE) 会议论文 OAI收割 MIPPR 2009 - Medical Imaging, Parallel Processing of Images, and Optimization Techniques: 6th International Symposium on Multispectral Image Processing and Pattern Recognition, October 30, 2009 - November 1, 2009, Yichang, China Chen Q.-P.; Li G.-J. 收藏 \| 浏览/下载：27/0 \| 提交时间：2013/03/25 This paper presents real-time MPEG-4 Simple Profile video compressing based on the DSP processor. The programming framework of video compressing is constructed using TMS320C6416 Microprocessor the architecture level optimizations are used to improve software pipeline. The system used DSP/BIOS to realize multi-thread scheduling. The whole system realizes high speed transition of a great deal of data. Experimental results show the encoder can realize real-time encoding of 768*576 TDS510 simulator and PC. It uses embedded real-time operating system DSP/BIOS and the API functions to build periodic function 25 frame/s video images. 2009 Copyright SPIE - The International Society for Optical Engineering. tasks and interruptions etcs. Realize real-time video compressing. To the questions of data transferring among the system. Based on the architecture of the C64x DSP utilized double buffer switched and EDMA data transfer controller to transit data from external memory to internal and realize data transition and processing at the same time
	Real-time quality control on a smart camera (EI CONFERENCE) 会议论文 OAI收割 ICO20: Optical Information Processing, August 21, 2005 - August 26, 2005, Changchun, China Xiao C.; Zhou H.; Li G.; Hao Z. 收藏 \| 浏览/下载：31/0 \| 提交时间：2013/03/25 A smart camera is composed of a video sensing high-level video processing communication and other affiliations within a single device. Such cameras are very important devices in quality control systems. This paper presents a prototyping development of a smart camera for quality control. The smart camera is divided to four parts: a CMOS sensor a digital signal processor (DSP) a CPLD and a display device. In order to improving the processing speed low-level and high-level video processing algorithms are discussed to the embedded DSP-based platforms. The algorithms can quickly and automatic detect productions' quality defaults. All algorithms are tested under a Matlab-based prototyping implementation and migrated to the smart camera. The smart camera prototype automatic processes the video data and streams the results of the video data to the display devices and control devices. Control signals are send to produce-line to adjust the producing state within the required real-time constrains.
	Evaluation and choice of various branch predictors for low-power embedded processor 期刊论文 OAI收割 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2003, 卷号: 18, 期号: 6, 页码: 833-838 作者: Fan, DR; Yang, HB; Gao, GR; Zhao, RC \| 收藏 \| 浏览/下载：15/0 \| 提交时间：2019/12/16 branch predictor embedded processor