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	Hidden Markov Model Approach for Software Reliability Estimation with Logic Error 期刊论文 OAI收割 International Journal of Automation and Computing, 2020, 卷号: 17, 期号: 2, 页码: 305-320 作者: R. Bharathi; R. Selvarani \| 收藏 \| 浏览/下载：20/0 \| 提交时间：2021/02/22 Hidden Markov model (HMM) reliability logic error safety critical software failure.
	Uncertainty due to DEM error in landslide susceptibility mapping SCI/SSCI论文 OAI收割 2013 Qin C. Z.; Bao L. L.; Zhu A. X.; Wang R. X.; Hu X. M. 收藏 \| 浏览/下载：46/0 \| 提交时间：2014/12/24 DEM error landslide susceptibility mapping error propagation Monte Carlo simulation uncertainty 3 gorges area digital elevation models logistic-regression hazard assessment yangtze-river fuzzy-logic gis propagation knowledge china
	Woulda, coulda, shoulda: The evaluation and the impact of the alternative outcome 期刊论文 OAI收割 PSYCHOPHYSIOLOGY, 2011, 卷号: 48, 期号: 10, 页码: 1354-1360 作者: Gu, Ruolei; Wu, Tingting; Jiang, Yang; Luo, Yue-Jia 收藏 \| 浏览/下载：18/0 \| 提交时间：2015/09/08 Decision making Outcome evaluation Alternative outcome Feedback-related negativity (FRN) Logic error Counterfactual thinking
	A new approach to realize UART (EI CONFERENCE) 会议论文 OAI收割 2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, August 12, 2011 - August 14, 2011, Harbin, China 作者: Wang Y.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：36/0 \| 提交时间：2013/03/25 In order to connect DSP which has synchronous serial ports to the devices implementing asynchronous communications protocol a method to implement UART communications based on programmable logic device is proposed in the paper. In the proposed method the core function of UART is integrated in CPLD with VHDL. Firstly UART data frame format and operational principle of UART were introduced after reviewing some methods to realize UART. The methods to implement UART transmitter UART receiver and baudrate generator using VHDL were illustrated in detail. Then pre-simulation and synthesize of VHDL program were executed. Finally the test with bit error rate was carried out on physical system. Experimental results indicate that 75 percent of the GLB are used by UART and the bit error rate is less than 109. The experiment was implemented utilizing the RS-422 protocol and the baudrate is 62.5kb/s. The proposed method can satisfy the system requirements of high integration stabilization low bit error rate strong anti-jamming and low cost. 2011 IEEE.
	bounded model checking of actl formulae 会议论文 OAI收割 3rd International Symposium on Theoretical Aspects of Software Engineering, Tianjin, PEOPLES R CHINA, JUL 29-31, Chen Wei; Zhang Wenhui \| 收藏 \| 浏览/下载：23/0 \| 提交时间：2011/03/20 bounded model checking encoding method bounded model verification computation tree logic error-hunting encoding formal logic formal verification program debugging tree data structures
	Decoherence and relevant universality in quantum algorithms via a dynamic theory for quantum measurement 期刊论文 OAI收割 PHYSICAL REVIEW A, 1998, 卷号: 58, 期号: 3, 页码: 1810-1821 作者: Zhan, H; Sun, CP; Liu, XF; Sun, CP , Acad Sinica, Inst Theoret Phys, POB 2735, Beijing 100080, Peoples R China. \| 收藏 \| 浏览/下载：32/0 \| 提交时间：2012/08/29 Wave-function Collapse Error-correcting Codes Dissipative System Computers Computation Realization Coherence Evolution Model Logic
	标记逻辑程序理论研究:说明语义与过程语义学位论文 OAI收割工学博士, 中国科学院自动化研究所: 中国科学院自动化研究所, 1994 作者: 周生炳收藏 \| 浏览/下载：52/0 \| 提交时间：2015/09/02 非单调推理容错推理标记逻辑程序支持模型诱导序列不循环程序多次极限多重极限表达式的复盖分解和划分 SLD-博弈树删除策略依赖团 nonmonotonic reasoning error-tolerated reasoning annotated logic program acyclic program supported model induced sequence coveri