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Covariance-Based Joint Device Activity and Delay Detection in Asynchronous mMTC 期刊论文  OAI收割
IEEE SIGNAL PROCESSING LETTERS, 2022, 卷号: 29, 页码: 538-542
作者:  
Wang, Zhaorui;  Liu, Ya-Feng;  Liu, Liang
  |  收藏  |  浏览/下载:58/0  |  提交时间:2022/04/02
ERGODIC APPROXIMATION TO CHEMICAL REACTION SYSTEM WITH DELAY 期刊论文  OAI收割
SIAM JOURNAL ON NUMERICAL ANALYSIS, 2019, 卷号: 57, 期号: 1, 页码: 70-95
作者:  
Chen, Chuchu;  Liu, Di
  |  收藏  |  浏览/下载:24/0  |  提交时间:2020/01/10
ERROR ANALYSIS FOR D-LEAPING SCHEME OF CHEMICAL REACTION SYSTEM WITH DELAY 期刊论文  OAI收割
MULTISCALE MODELING & SIMULATION, 2017, 卷号: 15, 期号: 4, 页码: 1797-1829
作者:  
Chen, Chuchu;  Liu, Di
  |  收藏  |  浏览/下载:26/0  |  提交时间:2018/07/30
Multi-channel high-speed TDICCD image data acquisition and storage system (EI CONFERENCE) 会议论文  OAI收割
2010 International Conference on E-Product E-Service and E-Entertainment, ICEEE2010, November 7, 2010 - November 9, 2010, Henan, China
作者:  
Li Y.;  Li Y.;  Li Y.;  Li Y.
收藏  |  浏览/下载:26/0  |  提交时间:2013/03/25
For multi-channel high-speed image data of certain space remote sensing camera  this paper proposed a new image data acquisition and storage system. First of all  the system uses Field-Programmable Gate Array(FPGA) controlling synchronous dynamic random access memory(SDRAM) array to realize the cache of image data  then according to the received commands  sends certain channel's image data to the acquisition card to write the image data into SCSI hard disk and implements the final storage. A Time Delay Integral Charge Couple Device(TDICCD) image data acquisition and storage system with five channels is developed  pixel clock rate is up to 96MHz  total effective data rate is up to 2.88Gb/s  single channel storage depth is up to 7810 lines. The experimental results indicate that this system work stably  high effectively which can meet the requirement of acquisition and storage of multi-channel high-speed TDICCD image data. 2010 IEEE.  
网络控制系统控制器设计和稳定性分析 学位论文  OAI收割
工学博士, 中国科学院自动化研究所: 中国科学院研究生院, 2009
作者:  
郭新兰
收藏  |  浏览/下载:57/0  |  提交时间:2015/09/02
Driving techniques for high frame rate CCD camera (EI CONFERENCE) 会议论文  OAI收割
Electronic Imaging and Multimedia Technology V, November 12, 2007 - November 15, 2007, Beijing, China
Guo W.; Jin L.; Xiong J.
收藏  |  浏览/下载:29/0  |  提交时间:2013/03/25
This paper describes a high-frame rate CCD camera capable of operating at 100 frames/s. This camera utilizes Kodak KAI-0340  an interline transfer CCD with 640(vertical)480(horizontal) pixels. Two output ports are used to read out CCD data and pixel rates approaching 30 MHz. Because of its reduced effective opacity of vertical charge transfer registers  interline transfer CCD can cause undesired image artifacts  such as random white spots and smear generated in the registers. To increase frame rate  a kind of speed-up structure has been incorporated inside KAI-0340  then it is vulnerable to a vertical stripe effect. The phenomena which mentioned above may severely impair the image quality. To solve these problems  some electronic methods of eliminating these artifacts are adopted. Special clocking mode can dump the unwanted charge quickly  then the fast readout of the images  cleared of smear  follows immediately. Amplifier is used to sense and correct delay mismatch between the dual phase vertical clock pulses  the transition edges become close to coincident  so vertical stripes disappear. Results obtained with the CCD camera are shown.