High bandwidth memory interface design based on DDR3 SDRAM and FPGA
文献类型：会议论文
| 作者 | Wang BP(王宝坡); Du JS(杜劲松) ; Bi X(毕欣); Tian X(田星)
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| 出版日期 | 2015 |
| 会议名称 | 12th International SoC Design Conference (ISOCC 2015) |
| 会议日期 | November 2-5, 2015 |
| 会议地点 | Gyeongju, South Korea |
| 关键词 | Memory interface DDR3 FPGA IP High bandwidth |
| 页码 | 253-254 |
| 中文摘要 | This work presented the high bandwidth memory interface design based on DDR3 SDRAM using external memory IP core provided by FPGA devices. The structure and configuration of IP core was introduced and the simulation on soft and hard IP was carried out with the access controller designed. The maximum transmission bandwidth of the memory interface based on the soft and hard IP respectively reached 19.2Gbps and 25.6Gbps. Finally, the reliability of the interface controller was verified by downloading the program to the DAQ board and observing the internal signals. |
| 收录类别 | EI ; CPCI（ISTP） |
| 产权排序 | 1 |
| 会议录 | 12th International SoC Design Conference (ISOCC 2015)
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| 语种 | 英语 |
| WOS记录号 | WOS:000380449100116 |
| 源URL | [http://ir.sia.cn/handle/173321/17364]  |
| 专题 | 沈阳自动化研究所_智能检测与装备研究室 |
| 推荐引用方式 GB/T 7714 | Wang BP,Du JS,Bi X,et al. High bandwidth memory interface design based on DDR3 SDRAM and FPGA[C]. 见:12th International SoC Design Conference (ISOCC 2015). Gyeongju, South Korea. November 2-5, 2015. |
入库方式： OAI收割
来源：沈阳自动化研究所
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