Transaction level model of NoC based on SystemC
文献类型：会议论文
| 作者 | Wang J(王剑) ; Wang H(王宏); Yang ZJ(杨志家)
|
| 出版日期 | 2009 |
| 会议名称 | IEEE 8th International Conference on ASIC |
| 会议日期 | October 20-23, 2009 |
| 会议地点 | Changsha, China |
| 关键词 | network on chip transaction-level model SystemC |
| 页码 | 97-100 |
| 中文摘要 | This paper presents a transaction-level on-chip communication network model, including routers and links, which can be easily employed in a system-level system-on-chip simulation framework for early functional verification and architecture analysis. The model is capable of providing NoC's latency and throughput information during simulating process and developed in SystemC to achieve high simulation speed(1). |
| 收录类别 | EI ; CPCI（ISTP） |
| 产权排序 | 1 |
| 会议主办者 | IEEE Beijing Sect, Fudan Univ, IEEE China Council, Natl Univ Def Tech, IEEE CAS, IEEE SSCS, Chinese Inst Elect |
| 会议录 | 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS
 |
| 会议录出版者 | IEEE |
| 会议录出版地 | NEW YORK |
| 语种 | 英语 |
| ISBN号 | 978-1-4244-3868-6 |
| WOS记录号 | WOS:000275924100020 |
| 源URL | [http://ir.sia.cn/handle/173321/8426]  |
| 专题 | 沈阳自动化研究所_工业信息学研究室 |
| 推荐引用方式 GB/T 7714 | Wang J,Wang H,Yang ZJ. Transaction level model of NoC based on SystemC[C]. 见:IEEE 8th International Conference on ASIC. Changsha, China. October 20-23, 2009. |
入库方式： OAI收割
来源：沈阳自动化研究所
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