Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence
文献类型：会议论文
| 作者 | Wang BP(王保坡) ; Du JS(杜劲松); Tian X(田星); Bi X(毕欣)
|
| 出版日期 | 2014 |
| 会议名称 | 2014 4th International Conference on Applied Mechanics, Materials and Manufacturing (ICA3M 2014)(Applied Mechanics and Materials) |
| 会议日期 | August 23-24, 2014 |
| 会议地点 | Shenzhen, China |
| 关键词 | PCB Design DDR3 Fly-by Leveling-free Source synchronous |
| 页码 | 1447-1453 |
| 中文摘要 | For the requirements of different bus signals from high speed PCB with DDR3 components based on fly-by topology structure, coping strategies have been proposed respectively. For the address or command bus, a leveling-free strategy has been proposed. It shows that the phase difference can be nearly zero through reasonable constraints on PCB design. The strategy was applied to the clock bus and achieved good performance, combining with the rules of signal integrity. For the data bus, the timing sequence on source synchronous has been analyzed and the time margin was calculated. The reasonability of the design was verified through the simulation result with Cadence. |
| 收录类别 | EI ; CPCI（ISTP） |
| 产权排序 | 1 |
| 会议录 | Applied Mechanics and Materials
 |
| 会议录出版者 | Trans Tech Publications |
| 会议录出版地 | Zurich-Durnten, Switzerland |
| 语种 | 英语 |
| ISSN号 | 1662-7482 |
| WOS记录号 | WOS:000348385100290 |
| 源URL | [http://ir.sia.cn/handle/173321/15346]  |
| 专题 | 沈阳自动化研究所_智能检测与装备研究室 |
| 推荐引用方式 GB/T 7714 | Wang BP,Du JS,Tian X,et al. Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence[C]. 见:2014 4th International Conference on Applied Mechanics, Materials and Manufacturing (ICA3M 2014)(Applied Mechanics and Materials). Shenzhen, China. August 23-24, 2014. |
入库方式： OAI收割
来源：沈阳自动化研究所
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