Writing a RVM-Compliant AHB Master Transactor
文献类型：会议论文
| 作者 | Yang ZJ(杨志家) ; Zhang YF(张玉峰); Li SG(李肃刚); Chen, Jason C.
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| 出版日期 | 2005 |
| 会议名称 | 2005 SNUG论文集 |
| 会议地点 | Beijing |
| 关键词 | AHB Master DesignWare VIP RVM base class transactor rvm_xactor |
| 中文摘要 | The use of AMBA-based buses is ubiquitous in today’s System On Chips (SoC). Verification IPs (VIP) are effective in generating stimuli for block-level, subsystem-level, and top-level testbenches. The reference verification methodology (RVM) and its base class library for Vera help verification engineers to build a testbench that enables constrained random verification and promotes re-use. Keeping the transactors in an RVM style makes them have the same look and feel and consequently make them easier to use (e.g. when writing tests). This paper discusses how an RVM compliant AHB master transactor is designed using the DesignWare AHB Master VIP and demonstrates how to configure it for the testbench and how to create test stimuli using the transactor |
| 产权排序 | 1 |
| 会议主办者 | Synopsys |
| 会议录 | 2005 SNUG论文集
 |
| 会议录出版者 | Synopsys |
| 会议录出版地 | Beijing |
| 语种 | 英语 |
| 源URL | [http://ir.sia.cn/handle/173321/9196]  |
| 专题 | 沈阳自动化研究所_工业信息学研究室_工业控制系统研究室 |
| 推荐引用方式 GB/T 7714 | Yang ZJ,Zhang YF,Li SG,et al. Writing a RVM-Compliant AHB Master Transactor[C]. 见:2005 SNUG论文集. Beijing. |
入库方式： OAI收割
来源：沈阳自动化研究所
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