机构

• 苏州纳米技术与纳米仿... [1]
• 长春光学精密机械与物... [1]
• 西双版纳热带植物园 [1]

采集方式

• OAI收割 [3]

内容类型

• 期刊论文 [2]
• 会议论文 [1]

发表日期

• 2020 [1]
• 2016 [1]
• 2011 [1]

学科主题

• Geoscience... [1]
• Soil Scien... [1]
• Water Reso... [1]

筛选

浏览/检索结果: 共3条，第1-3条 帮助 条数/页： 5101520253035404550556065707580859095100 排序方式： 请选择题名升序题名降序提交时间升序提交时间降序作者升序作者降序发表日期升序发表日期降序 Soil organic matter as affected by the conversion of natural tropical rainforest to monoculture rubber plantations under acric ferralsols 期刊论文  OAI收割 CATENA, 2020, 卷号: 195, 期号: x, 页码: - 作者:  Balasubramanian, D.;  Zhang, Yi-Ping;  Grace, John;  Sha, Li-Qing;  Jin, Yanqiang   |  收藏  |  浏览/下载：37/0  |  提交时间：2021/02/05 LAND-USE CHANGES  DENSITY FRACTIONS  STABILIZATION MECHANISMS  PHYSICAL FRACTIONATION  LITTER DECOMPOSITION  TREE PLANTATIONS  CARBON STOCKS  NITROGEN  C-13  EFFICIENCY   Coassembly of Tobacco Mosaic Virus Coat Proteins into Nanotubes with Uniform Length and Improved Physical Stability 期刊论文  OAI收割 ACS APPLIED MATERIALS & INTERFACES, 2016, 卷号: 8, 期号: 21, 页码: 13192-13196 作者:  Zhou, K(周堃);  Eiben, S;  Wang, QB(王强斌) 收藏  |  浏览/下载：47/0  |  提交时间：2017/03/11 chimerical scaffold   coassembly   disulfide bond   length-controllability   physical stabilization   tobacco mosaic virus   A new approach to realize UART (EI CONFERENCE) 会议论文  OAI收割 2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, August 12, 2011 - August 14, 2011, Harbin, China 作者:  Wang Y.;  Wang Y.;  Wang Y.;  Wang Y.;  Wang Y. 收藏  |  浏览/下载：35/0  |  提交时间：2013/03/25 In order to connect DSP which has synchronous serial ports to the devices implementing asynchronous communications protocol  a method to implement UART communications based on programmable logic device is proposed in the paper. In the proposed method  the core function of UART is integrated in CPLD with VHDL. Firstly  UART data frame format and operational principle of UART were introduced after reviewing some methods to realize UART. The methods to implement UART transmitter  UART receiver and baudrate generator using VHDL were illustrated in detail. Then pre-simulation and synthesize of VHDL program were executed. Finally  the test with bit error rate was carried out on physical system. Experimental results indicate that 75 percent of the GLB are used by UART  and the bit error rate is less than 109. The experiment was implemented utilizing the RS-422 protocol and the baudrate is 62.5kb/s. The proposed method can satisfy the system requirements of high integration  stabilization  low bit error rate  strong anti-jamming and low cost. 2011 IEEE.