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	Realization of auto-focusing system for cameras based on TMS320F2812 DSP (EI CONFERENCE) 会议论文 OAI收割 2nd Annual Conference on Electrical and Control Engineering, ICECE 2011, September 16, 2011 - September 18, 2011, Yichang, China 作者: Zhang T. 收藏 \| 浏览/下载：28/0 \| 提交时间：2013/03/25 Focusing systems play an important role in a variety of optical measurements and detection instruments. In this paper several kinds of auto-focusing methods were described and the relevant focusing evaluation functions were introduced based on image processing methods. An auto-focusing system based on image processing was designed by using the TMS320F2812 digital signal processing chip as a platform. Moreover some problem and solutions about auto-focusing system was demonstrated. The system designed in this paper can find the good image plane in 10 steps (about 5 second) thus it can meet the requirements of practical applications. 2011 IEEE.
	Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China 作者: Sun H.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：33/0 \| 提交时间：2013/03/25 CCD noises and their causes are analyzed. Methods to control these noises such as Correlated Double Sampling (CDS) filtering cooling clamping and calibration are proposed. To improve CCD sensor's performances the IC called Analog Front End (AFE) integration of CDS clamping Programmable Gain Amplifier (PGA) offset and ADC which can fulfill the CDS and analog-to-digital conversion is employed to process the output signal of CCD. Based on the noise control approaches the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator for both CCD and AFE and (2) interface helping to analysis and transfer control command and status information between MCU controller and drive pulse generator or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed such as clock generator for CCD and AFE MCU interface AFE serial interface output interface CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip Xilinx XC2C256-6-VQ100 with 20MHz pixel frequency and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last the design result is presented.
	A new spaceborne compression approach for remote sensing imagery (EI CONFERENCE) 会议论文 OAI收割 ICO20: Remote Sensing and Infrared Devices and Systems, August 21, 2005 - August 26, 2005, Changchun, China 作者: Xu S. 收藏 \| 浏览/下载：31/0 \| 提交时间：2013/03/25 After analyzing advantages and disadvantages of these typical encoding methods: SPIHT and VQ a "DWT+MRLE" approach for spaceborne data compression was proposed in this paper. This approach includes two steps: Discrete Wavelet Transform (DWT) and Modified Run Length Encoding (MRLE). The former used CDF9/7 biorthogonal wavelet filters to powerfully get rid of correlation between pixels in imagery. The later put enlightening information into the lowest bit of some key-position transform coefficients. Consequently CDF9/7 and MRLE together make hardware platform remain high real-time capability and help reconstructed images keep good fidelity with PSNR being about 40dB compared with the original ones. Comparison between experimentations on SPOT4's low-spatial-resolution (10m) imagery and Ikonos2's high-spatial-resolution (1m) imagery shows this "DWT+MRLE" method having better performance for remote-sensed imagery especially those of higher resolution. Although inferior to 8:1 Compression Ration (CR) here near 5:1 is greater than France SPOT5's 3:1 and American Ikonos2's 11:2.6 on-board data compression. More important this method having less computational amount is good for spaceborne capability of real time. The consumed time of different image size is also presented in this paper based on TI TMSC6416 DSP chip with 600MHz CPU cycle clock.
	High throughput microanalysis 期刊论文 OAI收割 PROGRESS IN CHEMISTRY, 2005, 卷号: 17, 期号: 4, 页码: 573-580 作者: Chen, Y \| 收藏 \| 浏览/下载：21/0 \| 提交时间：2019/04/09 High Throughput Microanalysis Chip-based Methods Surface Plasma Resonance Imaging
	module placement with boundary constraints using o-tree representation 会议论文 OAI收割 IEEE International Symposium on Circuits and Systems, PHOENIX, AZ, MAY 26-29, Liu R; Hong XL; Dong SQ; Cai YC; Gu J; Cheng CK \| 收藏 \| 浏览/下载：18/0 \| 提交时间：2011/07/29 I/O pad connection O-tree representation VLSI physical design boundary constraints chip boundary placement layout generation linear computation effort module placement polynomial methods simulated annealing based algorithm circuit optimisation