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	Frequency control algorithm of domestic optically pumped small cesium clock based on optimal control theory 期刊论文 OAI收割 ACTA PHYSICA SINICA, 2024, 卷号: 73, 期号: 6, 页码: 11 作者: Song Hui-Jie; Dong Shao-Wu; Wang Xiang; Jiang Meng; Zhang Yu \| 收藏 \| 浏览/下载：5/0 \| 提交时间：2025/04/03 atomic clock state model linear quadratic Gaussian control Kalman filter atomic clock noise
	Scalable Clock Synchronization Analysis: A Symmetric Noncooperative Output Feedback Tubes-MPC Approach 期刊论文 OAI收割 IEEE/CAA Journal of Automatica Sinica, 2020, 卷号: 7, 期号: 6, 页码: 1604-1626 作者: Ting Wang; Xiaoquan Xu; Xiaoming Tang \| 收藏 \| 浏览/下载：23/0 \| 提交时间：2021/03/11 Affine system clock synchronization model predictive control output feedback
	The sequence measurement system of the IR camera (EI CONFERENCE) 会议论文 OAI收割 International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Infrared Imaging and Applications, May 24, 2011 - May 24, 2011, Beijing, China 作者: 收藏 \| 浏览/下载：35/0 \| 提交时间：2013/03/25 Currently the IR cameras are broadly used in the optic-electronic tracking optic-electronic measuring fire control and optic-electronic countermeasure field but the output sequence of the most presently applied IR cameras in the project is complex and the giving sequence documents from the leave factory are not detailed. Aiming at the requirement that the continuous image transmission and image procession system need the detailed sequence of the IR cameras the sequence measurement system of the IR camera is designed and the detailed sequence measurement way of the applied IR camera is carried out. The FPGA programming combined with the SignalTap online observation way has been applied in the sequence measurement system and the precise sequence of the IR camera's output signal has been achieved the detailed document of the IR camera has been supplied to the continuous image transmission system image processing system and etc. The sequence measurement system of the IR camera includes CameraLink input interface part LVDS input interface part FPGA part CameraLink output interface part and etc thereinto the FPGA part is the key composed part in the sequence measurement system. Both the video signal of the CmaeraLink style and the video signal of LVDS style can be accepted by the sequence measurement system and because the image processing card and image memory card always use the CameraLink interface as its input interface style the output signal style of the sequence measurement system has been designed into CameraLink interface. The sequence measurement system does the IR camera's sequence measurement work and meanwhile does the interface transmission work to some cameras. Inside the FPGA of the sequence measurement system the sequence measurement program the pixel clock modification the SignalTap file configuration and the SignalTap online observation has been integrated to realize the precise measurement to the IR camera. Te sequence measurement program written by the verilog language combining the SignalTap tool on line observation can count the line numbers in one frame pixel numbers in one line and meanwhile account the line offset and row offset of the image. Aiming at the complex sequence of the IR camera's output signal the sequence measurement system of the IR camera accurately measures the sequence of the project applied camera supplies the detailed sequence document to the continuous system such as image processing system and image transmission system and gives out the concrete parameters of the fval lval pixclk line offset and row offset. The experiment shows that the sequence measurement system of the IR camera can get the precise sequence measurement result and works stably laying foundation for the continuous system. 2011 Copyright Society of Photo-Optical Instrumentation Engineers (SPIE).
	运动控制网络的若干关键特性分析会议论文 OAI收割 2011 International Conference on Electric Information and Control Engineering, Wuhan, China, April 15-17, 2011 作者: Zhou D(周侗); Hu JT(胡静涛); Yang ZJ(杨志家) 收藏 \| 浏览/下载：18/0 \| 提交时间：2012/06/06 motion-control network-scheduling clock-synchronization
	Design and implementation of Electro-optical Countermeasure Hardware-in-the-loop simulation system based on HLA (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China 作者: Guo J.; Cui S.; Guo J.; Li Y.; Li Y. 收藏 \| 浏览/下载：21/0 \| 提交时间：2013/03/25 In this paper the Electro-optical Countermeasure Hardware-in-the-loop simulation system is introduced which highlight to problem: real-time control and acquisition of communications data. We discuss the real-time mechanism by the combination of HLA time management mechanism for real-time data communication and out clock and the double buffer of the acquisition method which ensures high frequency real-time data communications and high data reliability integrity. The tested data is shown that the Electro-optical Countermeasure Hardware-in-the-Ioop simulation system work properly. 2010 IEEE.
	Research of computer control system for laser warning HWIL simulation (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China 作者: Wang J.-J. 收藏 \| 浏览/下载：18/0 \| 提交时间：2013/03/25 A computer control system is proposed which is based on hardware-in-loop(HWIL) simulation test system. As an important sub-system in simulation test system the reality is the focus of the simulation system. The construction of the computer control system for laser warning based on HLA Distributed Simulation. By combining the outer clock and time stamp for data frame data interaction is triggered by outer clock the simulation process is propelled. The simulation terminal devices are also controlled by the outer clock. The simulation test is done by the above method. The result shows that the data interaction time less than lms and it meet the need of reality for control so it is effective. 2010 IEEE.
	Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China 作者: Sun H.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：30/0 \| 提交时间：2013/03/25 CCD noises and their causes are analyzed. Methods to control these noises such as Correlated Double Sampling (CDS) filtering cooling clamping and calibration are proposed. To improve CCD sensor's performances the IC called Analog Front End (AFE) integration of CDS clamping Programmable Gain Amplifier (PGA) offset and ADC which can fulfill the CDS and analog-to-digital conversion is employed to process the output signal of CCD. Based on the noise control approaches the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator for both CCD and AFE and (2) interface helping to analysis and transfer control command and status information between MCU controller and drive pulse generator or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed such as clock generator for CCD and AFE MCU interface AFE serial interface output interface CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip Xilinx XC2C256-6-VQ100 with 20MHz pixel frequency and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last the design result is presented.
	Security analysis of the generalized self-shrinking generator 期刊论文 iSwitch采集 Information and communications security, proceedings, 2004, 卷号: 3269, 页码: 388-400 作者: Zhang, B; Wu, HJ; Feng, DG; Bao, F 收藏 \| 浏览/下载：40/0 \| 提交时间：2019/05/10 Stream cipher Self-shrinking generator Clock control Fast correlation attack Linear feedback shift register