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	The design of high-speed optical fiber communication system based on PCI bus (EI CONFERENCE) 会议论文 OAI收割 2010 2nd IEEE International Conference on Advanced Management Science, ICAMS 2010, July 9, 2010 - July 11, 2010, Chengdu, China 作者: Zhang L.-G.; Zhang L.-G.; He X. 收藏 \| 浏览/下载：57/0 \| 提交时间：2013/03/25 In order to increase the transmission distance and reduce noise effectively a communication system with the optical fiber interface is developed in this paper. In the system the PCI bus is adopted as the connection bus between the underlying optical fiber transceiver module circuitry and host computer using the WDM driver. The FPGA is the core logic of the whole system responsible for data transmission and timing logic control. The module structure and the design method of the PCI bus the principle and the design of optical interface module and the bottom-driven development are described in this paper. The experiment results show that the system has basically meet requirement targets. It can achieve the maximum transfer rate of 40MBps when running in the DMA mode. With long transmission distance strong antiinterference and high scalability this system has stable and reliable performance. 2010 IEEE.
	Storage and compression design of high speed CCD (EI CONFERENCE) 会议论文 OAI收割 4th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 19, 2008 - November 21, 2008, Chengdu, China Cai X.; Zhai L. P. 收藏 \| 浏览/下载：61/0 \| 提交时间：2013/03/25 In current field of CCD measurement large area and high resolution CCD is used to obtain big measurement image so that speed and capacity of CCD requires high performance of later storage and process system. The paper discusses how to use SCSI hard disk to construct storage system and use DSPs and FPGA to realize image compression. As for storage subsystem Because CCD is divided into multiplex output SCSI array is used in RAID0 way. The storage system is composed of high speed buffer DMA controller control MCU SCSI protocol controller and SCSI hard disk. As for compression subsystem according to requirement of communication and monitor system the output is fixed resolution image and analog PAL signal. The compression means is JPEG2000 standard in which 9/7 wavelets in lifting format is used. 2 DSPs and FPGA are used to compose parallel compression system. The system is composed of FPGA pre-processing module DSP compression module video decoder module data buffer module and communication module. Firstly discrete wavelet transform and quantization is realized in FPGA. Secondly entropy coding and stream adaption is realized in DSPs. Last analog PAL signal is output by Video decoder. Data buffer is realized in synchronous dual-port RAM and state of subsystem is transfer to controller. Through subjective and objective evaluation the storage and compression system satisfies the requirement of system. 2009 SPIE.
	A Prototype of the Read-out Subsystem of the BESIII DAQ Based on PowerPC 期刊论文 OAI收割 Plasma Science & Technology, 2005, 期号: 5, 页码: 3065-3068 作者: Tao N(陶宁); Chu YP(初元萍); Jin G(金革); Zhao JW(赵京伟) 收藏 \| 浏览/下载：15/0 \| 提交时间：2015/12/21 BESIII DAQ readout system single board computer VMEbus DMA transfer
	A prototype of the read-out subsystem of the BESIII DAQ based on PowerPC 期刊论文 OAI收割 PLASMA SCIENCE & TECHNOLOGY, 2005, 卷号: 7, 期号: 5, 页码: 3065-3068 作者: Ning, T; Chu YP(初元萍); Zhao JW(赵京伟); Chu, YP; Ge, J 收藏 \| 浏览/下载：25/0 \| 提交时间：2016/06/29 BESIII DAQ readout system single board computer VMEbus DMA transfer