机构

• 长春光学精密机械与物... [1]
• 高能物理研究所 [1]
• 近代物理研究所 [1]

采集方式

• OAI收割 [3]

内容类型

• 期刊论文 [2]
• 会议论文 [1]

发表日期

• 2017 [1]
• 2016 [1]
• 2010 [1]

学科主题

筛选

浏览/检索结果: 共3条，第1-3条 帮助 条数/页： 5101520253035404550556065707580859095100 排序方式： 请选择题名升序题名降序提交时间升序提交时间降序作者升序作者降序发表日期升序发表日期降序 An active base designed in high-counting-rate applications for Hamamatsu R1924A photomultiplier tube 期刊论文  OAI收割 NUCLEAR SCIENCE AND TECHNIQUES, 2017, 卷号: 28, 页码: 5 作者:  Han, Rui;  Liu, Xing-Quan;  Luo, Fei;  Ren, Pei-Pei;  Lin, Wei-Ping   |  收藏  |  浏览/下载：39/0  |  提交时间：2018/05/31 Active Base  High Counting Rate  Hamamatsu R1924a Photomultiplier Tube   HEPS-BPIX, a single photon counting pixel detector with a high frame rate for the HEPS project 期刊论文  OAI收割 NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 2016, 卷号: 835, 页码: 169 作者:  Wei W(魏微);  Zhang J(张杰);  Ning Z(宁哲);  Lu YP(卢云鹏);  Fan L(樊磊)   |  收藏  |  浏览/下载：37/0  |  提交时间：2017/07/27 Pixel detector  Single photon counting  High frame rate  Synchrotron radiation  X-ray imaging  HEPS   The design of acquisition circuit for grating digital signal based on FPGA (EI CONFERENCE) 会议论文  OAI收割 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China 作者:  Wang W.-G. 收藏  |  浏览/下载：37/0  |  提交时间：2013/03/25 In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to  counting circuit  the results show that the design method will help improve the controlled object of measurement precision and control accuracy. 2010 IEEE.  we design a circuit based on FPGA to realize multiplier  kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as filtering  multiplier kam-to and counting. The main function of filter circuit is to eliminate the jitter and noise interference existing in the quadrate encoder signals. Kam-to multiplier circuit can accurately judge the full cycle and half-cycle of incremental encoder  at the same time can make fourfold multiplier. Counting circuit can use IP cores owned by Quartus II which is not restricted on the median. At last  timing simulation based on Modelsim carried on the three modules