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	Channel characteristics and interface drive of single core bus of while drilling in intelligent guide drilling 期刊论文 OAI收割 CHINESE JOURNAL OF GEOPHYSICS-CHINESE EDITION, 2023, 卷号: 66, 期号: 1, 页码: 131-138 作者: Zhen QiHui; Di QingYun; Wang YuLiang; Yang QuanMin \| 收藏 \| 浏览/下载：22/0 \| 提交时间：2023/03/30 Intelligent drilling Logging while drilling bus Working frequency Interface drive
	Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者: Wang Y.; Wang Y.; Wang Y.; Sun H.; Sun H. 收藏 \| 浏览/下载：37/0 \| 提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition these functions that adjustments of exposure beginning time integral time AOI (Area of Interest) output and so on are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip) and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate low power intelligent and miniaturization digital video camera.
	Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China 作者: Sun H.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：30/0 \| 提交时间：2013/03/25 CCD noises and their causes are analyzed. Methods to control these noises such as Correlated Double Sampling (CDS) filtering cooling clamping and calibration are proposed. To improve CCD sensor's performances the IC called Analog Front End (AFE) integration of CDS clamping Programmable Gain Amplifier (PGA) offset and ADC which can fulfill the CDS and analog-to-digital conversion is employed to process the output signal of CCD. Based on the noise control approaches the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator for both CCD and AFE and (2) interface helping to analysis and transfer control command and status information between MCU controller and drive pulse generator or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed such as clock generator for CCD and AFE MCU interface AFE serial interface output interface CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip Xilinx XC2C256-6-VQ100 with 20MHz pixel frequency and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last the design result is presented.