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	End-to-end learning interpolation for object tracking in low frame-rate video 期刊论文 OAI收割 IET Image Processing, 2020, 卷号: 14, 期号: 6, 页码: 1066-1072 作者: Liu, Liqiang; Cao, Jianzhong \| 收藏 \| 浏览/下载：65/0 \| 提交时间：2020/05/20 video signal processing learning (artificial intelligence) object tracking interpolation mobile computing low frame rates implicit video frame interpolation sub-network object tracking low frame-rate video high frame-rate latent video effective end-to-end optimisation frame rate tracking accuracy semantic video analytics end-to-end learning interpolation subsequent semantic analytics bandwidth constraints analytics performance
	Low complexity encoder optimization for HEVC 期刊论文 OAI收割 JOURNAL OF VISUAL COMMUNICATION AND IMAGE REPRESENTATION, 2016, 卷号: 35, 页码: 120-131 作者: Wang, Shanshe; Luo, Falei; Ma, Siwei; Zhang, Xiang; Wang, Shiqi \| 收藏 \| 浏览/下载：40/0 \| 提交时间：2019/12/13 HEVC Low complexity Intra mode decision CU splitting Reference frame selection Rate distortion optimization Video coding Encoder optimization
	A Robust Tracking System for Low Frame Rate Video 期刊论文 OAI收割 INTERNATIONAL JOURNAL OF COMPUTER VISION, 2015, 卷号: 115, 期号: 3, 页码: 279-304 作者: Zhang, Xiaoqin; Hu, Weiming; Xie, Nianhua; Bao, Hujun; Maybank, Stephen 收藏 \| 浏览/下载：32/0 \| 提交时间：2016/01/18 Low frame rate Tracking Dominant color Bin-ratio matching metric Particle swarm optimization
	A new approach to realize UART (EI CONFERENCE) 会议论文 OAI收割 2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, August 12, 2011 - August 14, 2011, Harbin, China 作者: Wang Y.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：33/0 \| 提交时间：2013/03/25 In order to connect DSP which has synchronous serial ports to the devices implementing asynchronous communications protocol a method to implement UART communications based on programmable logic device is proposed in the paper. In the proposed method the core function of UART is integrated in CPLD with VHDL. Firstly UART data frame format and operational principle of UART were introduced after reviewing some methods to realize UART. The methods to implement UART transmitter UART receiver and baudrate generator using VHDL were illustrated in detail. Then pre-simulation and synthesize of VHDL program were executed. Finally the test with bit error rate was carried out on physical system. Experimental results indicate that 75 percent of the GLB are used by UART and the bit error rate is less than 109. The experiment was implemented utilizing the RS-422 protocol and the baudrate is 62.5kb/s. The proposed method can satisfy the system requirements of high integration stabilization low bit error rate strong anti-jamming and low cost. 2011 IEEE.
	Design of driving circuit for binocular CCD image system (EI CONFERENCE) 会议论文 OAI收割 5th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optoelectronic Materials and Devices for Detector, Imager, Display, and Energy Conversion Technology, April 26, 2010 - April 29, 2010, Dalian, China 作者: Zhang X.; Zhang X.; Zhang X. 收藏 \| 浏览/下载：40/0 \| 提交时间：2013/03/25 The paper designs a driving circuit of high sensitive wide dynamic and high signal-to-noise ratio for binocular CCD imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Inner structure and driving timing of the FTF5066M sensor are presented. Field Programmable Gate Array (FPGA) is used as the main device to accomplish the timing design of the circuits and power driver control of the two sensors. By using the Correlated Double Sampling (CDS) technique the video noise is reduced and the SNR of the system is increased. A 12- bit A/D converter is used to improve the image quality. The output rate of the imaging system designed with integrated chip can reach to 1.3 frames per second through bi-channel. For its good performance low power consumption and small volume the driving system can be applied to aeronautics and astronautics field. With a further improvement a maximum data output rate of 2.7 frames per second can be reached through all the eight channels of the two CCDs. 2010 Copyright SPIE - The International Society for Optical Engineering.
	Panoramic aerial camera image motion measurement using a hybrid system (EI CONFERENCE) 会议论文 OAI收割 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, July 9, 2010 - July 11, 2010, Chengdu, China 作者: Jia P. 收藏 \| 浏览/下载：26/0 \| 提交时间：2013/03/25 Image motion compensation is significantly important for aerial camera photograph. To execute the compensation we must determine the image motion exactly. This paper proposes a method of real-time image motion measurement for panoramic aerial cameras based on image processing using a hybrid system. Two cameras are simultaneously used in the hybrid system. One main linear CCD for imaging while the other auxiliary low resolution high frame rate area CCD for determining the image motion based on 2D spatial correlation. The demanding computational requirements for the real-time 2D spatial correlation are covered by a joint transform optical correlator. Simulation test results show that the accuracy is improved and the measurement error is within 0.2 pixels for input images with SNR=1 dB. 2010 IEEE.
	Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者: Wang Y.; Wang Y.; Wang Y.; Sun H.; Sun H. 收藏 \| 浏览/下载：35/0 \| 提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition these functions that adjustments of exposure beginning time integral time AOI (Area of Interest) output and so on are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip) and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate low power intelligent and miniaturization digital video camera.
	Research on tracking approach to low-flying weak small target near the sea (EI CONFERENCE) 会议论文 OAI收割 ICO20: Optical Information Processing, August 21, 2005 - August 26, 2005, Changchun, China 作者: Xue X.-C. 收藏 \| 浏览/下载：32/0 \| 提交时间：2013/03/25 Automatic target detection is very difficult in complicate background of sea and sky because of the clutter caused by waves and clouds nearby the sea-level line. In this paper in view of the low-flying target near the sea is always above the sea-level line we can first locate the sea-level line and neglect the image data beneath the sea-level line. Thus the noise under the sea-level line can be suppressed and the executive time of target segmentation is also much reduced. A new method is proposed which first uses neighborhood averaging method to suppress background and enhance targets so as to increase SNR and then uses the multi-point multi-layer vertical Sobel operator combined with linear least squares fitting to locate the sea-level line lastly uses the centroid tracking algorithm to detect and track the target. In the experiment high frame rate and high-resolution digital CCD camera and high performance DSP are applied. Experimental results show that this method can efficiently locate the sea-level line on various conditions of lower contrast and eliminate the negative impact of the clutter caused by waves and clouds and capture and track target real-timely and accurately.
	Design of an improved data signal timing for an amorphous silicon active-matrix organic LED display (EI CONFERENCE) 会议论文 OAI收割 ICO20: Display Devices and Systems, August 21, 2005 - August 26, 2005, Changchun, China 作者: Zhang Z.-W. 收藏 \| 浏览/下载：18/0 \| 提交时间：2013/03/25 The most critical issue in the design of an active matrix organic light emitting diode (AM-OLED) display pixel is the pixel to the pixel luminance uniformity. By substituting four-thin film transistor (TFT) pixel circuit for two-TFT pixel circuit the luminous uniformity has great improved but it requires more components than the two-TFT pixel circuit. There are some barriers needed to resolve to utilize hydrogenated amorphous silicon transistor to lit OLED such as low field effect mobility low output current and threshold voltage shift. In this article a two-a-Si:H TFT pixel circuit was designed which consisted of one named switching TFT and the other named driving TFT. The driving TFT gate line structure modified and a data signal timing improved were reported. The modified driving TFT can provide enough current about 30 microampere to lit OLED and the novel data signal timing can provide a constant current to OLED by restraining the driving TFT threshold voltage variation. In the novel data signal timing the control signals to the driving TFT gate include a data signal and a reverse data signal. The signals alteration is performed either at a frame rate or at a line rate. By experiments the driving TFT output current value is plotted as a function of the time in different reversed voltage value. When the magnitude of the positive data signal and the negative data signal is equal the variety of Vth is smallest about 1.28V after a fixed stressing time of 1.33104min which shows the novel data signal timing can improved the driving TFT output-input current stability.