机构

• 长春光学精密机械与物... [1]
• 南京天文光学技术研究... [1]
• 近代物理研究所 [1]

采集方式

• OAI收割 [3]

内容类型

• 会议论文 [3]

发表日期

• 2013 [1]
• 2008 [1]
• 2006 [1]

学科主题

• 天文技术与方法::自... [1]
• 天文望远镜::郭守敬... [1]
• 终端仪器::天文光谱... [1]

筛选

浏览/检索结果: 共3条，第1-3条 帮助 条数/页： 5101520253035404550556065707580859095100 排序方式： 请选择题名升序题名降序提交时间升序提交时间降序作者升序作者降序发表日期升序发表日期降序 A Parallel BP Neural Network Based on the FPGA 会议论文  OAI收割 作者:  Qian Xiang-Ping;  Guo Yu-Hui;  Zhou De-Tai;  Zeng Xian-Qiang;  Yarlagadda, P   |  收藏  |  浏览/下载：28/0  |  提交时间：2018/08/20 Neural network  Field programmable gate array(FPGA)  Back Propagation algorithm  Parallel architecture  System On Programmable Chip(SOPC)   Design and realization of the real-time spectrograph controller for LAMOST based on FPGA 会议论文  OAI收割 Marseille, France, 2008-6-23 作者:  Zhongwen Hu;  Yongtian Zhu;  Zhen Wu;  Yi Chen;  Jianing Wang 收藏  |  浏览/下载：32/0  |  提交时间：2014/01/01 real-time spectrograph controller  Field Programmable Gate Array (FPGA)  System On Programmable Chip (SOPC)  NIOSⅡ  intellectual property (IP)  stepper motor  Ethernet network  LAMOST   Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文  OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者:  Wang Y.;  Wang Y.;  Wang Y.;  Sun H.;  Sun H. 收藏  |  浏览/下载：36/0  |  提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera  the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition  these functions that adjustments of exposure beginning time  integral time  AOI (Area of Interest) output and so on  are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip)  and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate  low power  intelligent and miniaturization digital video camera.