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	SOPC处理器的程序压缩与解压研究学位论文 OAI收割工学博士, 中国科学院自动化研究所: 中国科学院大学, 2015 作者: 涂吉收藏 \| 浏览/下载：65/0 \| 提交时间：2015/09/02 星载处理机代码压缩存储系统多字典可编程片上系统 On-board Computer Code Compression Memory System Multi-Dictionary System-on-a-Programmable-Chip
	Driving and image enhancement for CCD sensing image system (EI CONFERENCE) 会议论文 OAI收割 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, July 9, 2010 - July 11, 2010, Chengdu, China Zhang M.; Ren J. 收藏 \| 浏览/下载：28/0 \| 提交时间：2013/03/25 The paper designs a driving circuit of high sensitive wide dynamic for CCD sensing imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Field Programmable Gate Array (FPGA) is used as the main device to accomplish the timing design of the circuits and power driver control of the sensor. By using the Correlated Double Sampling (CDS) technique the video noise is reduced and the SNR of the system is increased. The output rate of the imaging system designed with integrated chip can reach to 1.3 frames per second through bi-channel output. We use the histogram specification to adjust the brightness of the captured image. And then use the median filtering to suppress the noise. The traditional gray mean gradient (GMG) and the objective evaluation method based on Human Visual System (HVS) used to verify the effect of image enhancement. 2010 IEEE.
	Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者: Wang Y.; Wang Y.; Wang Y.; Sun H.; Sun H. 收藏 \| 浏览/下载：37/0 \| 提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition these functions that adjustments of exposure beginning time integral time AOI (Area of Interest) output and so on are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip) and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate low power intelligent and miniaturization digital video camera.