中国科学院机构知识库网格系统: 检索

静止轨道星载差分吸收光谱仪CCD成像系统设计 期刊论文 OAI收割
光子学报, 2020, 卷号: 49
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收藏 | 浏览/下载：28/0 | 提交时间：2020/10/26

Remote sensing Imaging spectrometer Spectral image Array CCD Timing design 遥感探测成像光谱仪光谱图像面阵CCD 时序设计

The design of the data communication and display system based on GeoCOM technology (EI CONFERENCE) 会议论文 OAI收割
2012 5th International Symposium on Computational Intelligence and Design, ISCID 2012, October 28, 2012 - October 29, 2012, Hangzhou, China
Geng T.-W.; Wang Z.-Q.; Li D.-N.; Shen C.-W.

收藏 | 浏览/下载：26/0 | 提交时间：2013/03/25

The system is developed for the real-time data processing. The data include the sensor data from TS02 total station and the data from the CCD processing system. It was introduced that the TS02 total station which produced by the Leica company. The GeoCOM application interface which provided by Leica company for the client to exploit it was introduced. The main controller of the system is C8051F021. The protocol of I2C bus is simulated by software. System works in the timing interrupt way. The angle error is calculated and transferred to remote receive device. All data is displayed on LCD. The hardware and software design method is present. The system has been applied to the angle monitor equipment. The system is stable and reliable in practical application. 2012 IEEE.

The high timing resolution T0 system in IHEP E3 beam line 期刊论文 OAI收割
JOURNAL OF INSTRUMENTATION, 2012, 卷号: 7, 页码: P02013
作者: Qian S(钱森); Wang YF(王贻芳); Ning Z(宁哲); Qian, S; Wang, Y

收藏 | 浏览/下载：36/0 | 提交时间：2016/04/08

Timing detectors Detector design and construction technologies and materials Particle identification methods Noble-liquid detectors (scintillation ionization two-phase)

MicroFix: Using Timing Interpolation and Delay Sensors for Power Reduction 期刊论文 OAI收割
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2011, 卷号: 16, 期号: 2, 页码: 21
作者: Yan, Guihai; Han, Yinhe; Liu, Hui; Liang, Xiaoyao; Li, Xiaowei

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收藏 | 浏览/下载：16/0 | 提交时间：2019/12/16

Design Performance Reliability Power reduction fine-grained adaptability DVFS timing interpolation delay sensor

Design of driving circuit for binocular CCD image system (EI CONFERENCE) 会议论文 OAI收割
5th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optoelectronic Materials and Devices for Detector, Imager, Display, and Energy Conversion Technology, April 26, 2010 - April 29, 2010, Dalian, China
作者: Zhang X.; Zhang X.; Zhang X.

收藏 | 浏览/下载：45/0 | 提交时间：2013/03/25

The paper designs a driving circuit of high sensitive wide dynamic and high signal-to-noise ratio for binocular CCD imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Inner structure and driving timing of the FTF5066M sensor are presented. Field Programmable Gate Array (FPGA) is used as the main device to accomplish the timing design of the circuits and power driver control of the two sensors. By using the Correlated Double Sampling (CDS) technique the video noise is reduced and the SNR of the system is increased. A 12- bit A/D converter is used to improve the image quality. The output rate of the imaging system designed with integrated chip can reach to 1.3 frames per second through bi-channel. For its good performance low power consumption and small volume the driving system can be applied to aeronautics and astronautics field. With a further improvement a maximum data output rate of 2.7 frames per second can be reached through all the eight channels of the two CCDs. 2010 Copyright SPIE - The International Society for Optical Engineering.

Timing generator of scientific grade CCD camera and its implementation based on FPGA technology (EI CONFERENCE) 会议论文 OAI收割
5th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optoelectronic Materials and Devices for Detector, Imager, Display, and Energy Conversion Technology, April 26, 2010 - April 29, 2010, Dalian, China
作者: Li Y.; Li Y.; Li Y.; Li Y.

收藏 | 浏览/下载：37/0 | 提交时间：2013/03/25

The Timing Generator's functions of Scientific Grade CCD Camera is briefly presented: it generates various kinds of impulse sequence for the TDI-CCD video processor and imaging data output acting as the synchronous coordinator for time in the CCD imaging unit. The IL-E2TDI-CCD sensor produced by DALSA Co.Ltd. use in the Scientific Grade CCD Camera. Driving schedules of IL-E2 TDI-CCD sensor has been examined in detail the timing generator has been designed for Scientific Grade CCD Camera. FPGA is chosen as the hardware design platform schedule generator is described with VHDL. The designed generator has been successfully fulfilled function simulation with EDA software and fitted into XC2VP20-FF1152 (a kind of FPGA products made by XILINX). The experiments indicate that the new method improves the integrated level of the system. The Scientific Grade CCD camera system's high reliability stability and low power supply are achieved. At the same time the period of design and experiment is sharply shorted. 2010 Copyright SPIE - The International Society for Optical Engineering.

The design of acquisition circuit for grating digital signal based on FPGA (EI CONFERENCE) 会议论文 OAI收割
2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China
作者: Wang W.-G.

收藏 | 浏览/下载：43/0 | 提交时间：2013/03/25

In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to counting circuit the results show that the design method will help improve the controlled object of measurement precision and control accuracy. 2010 IEEE. we design a circuit based on FPGA to realize multiplier kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as filtering multiplier kam-to and counting. The main function of filter circuit is to eliminate the jitter and noise interference existing in the quadrate encoder signals. Kam-to multiplier circuit can accurately judge the full cycle and half-cycle of incremental encoder at the same time can make fourfold multiplier. Counting circuit can use IP cores owned by Quartus II which is not restricted on the median. At last timing simulation based on Modelsim carried on the three modules

Driving and image enhancement for CCD sensing image system (EI CONFERENCE) 会议论文 OAI收割
2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, July 9, 2010 - July 11, 2010, Chengdu, China
Zhang M.; Ren J.

收藏 | 浏览/下载：36/0 | 提交时间：2013/03/25

The paper designs a driving circuit of high sensitive wide dynamic for CCD sensing imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Field Programmable Gate Array (FPGA) is used as the main device to accomplish the timing design of the circuits and power driver control of the sensor. By using the Correlated Double Sampling (CDS) technique the video noise is reduced and the SNR of the system is increased. The output rate of the imaging system designed with integrated chip can reach to 1.3 frames per second through bi-channel output. We use the histogram specification to adjust the brightness of the captured image. And then use the median filtering to suppress the noise. The traditional gray mean gradient (GMG) and the objective evaluation method based on Human Visual System (HVS) used to verify the effect of image enhancement. 2010 IEEE.

The design of high-speed optical fiber communication system based on PCI bus (EI CONFERENCE) 会议论文 OAI收割
2010 2nd IEEE International Conference on Advanced Management Science, ICAMS 2010, July 9, 2010 - July 11, 2010, Chengdu, China
作者: Zhang L.-G.; Zhang L.-G.; He X.

收藏 | 浏览/下载：59/0 | 提交时间：2013/03/25

In order to increase the transmission distance and reduce noise effectively a communication system with the optical fiber interface is developed in this paper. In the system the PCI bus is adopted as the connection bus between the underlying optical fiber transceiver module circuitry and host computer using the WDM driver. The FPGA is the core logic of the whole system responsible for data transmission and timing logic control. The module structure and the design method of the PCI bus the principle and the design of optical interface module and the bottom-driven development are described in this paper. The experiment results show that the system has basically meet requirement targets. It can achieve the maximum transfer rate of 40MBps when running in the DMA mode. With long transmission distance strong antiinterference and high scalability this system has stable and reliable performance. 2010 IEEE.

An 8-channel, area-efficient, low-power audio sampling rate converter (EI CONFERENCE) 会议论文 OAI收割
9th International Conference on Electronic Measurement and Instruments, ICEMI 2009, August 16, 2009 - August 19, 2009, Beijing, China
作者: Liu Y.; Liu Y.; Liu Y.; Wang D.

收藏 | 浏览/下载：32/0 | 提交时间：2013/03/25

A novel 8-channle third area-efficient next a new Timing Division Multiplexer (TMD) scheme lowers clock working rate to minimum in order to save power a novel memory addressing scheme reduces 20% data memory at least. Experiments show proposed methods could not only saved hardware resources but also reduce power consumption low-power audio sampling rate converter is proposed in this paper so it is very suitable for consumer electronics. 2009 IEEE. conversion ratio is 2:1 and 4:1. Filter design and implementation are the key points for the converter. First excluded data and coefficients memories adopting multiplier-free Arithmetic Unit (AU) and rounding methods allows its realization in a cell area of only 0.038mm 2 in 0.18 m technology