机构

• 长春光学精密机械与物... [1]
• 上海天文台 [1]

采集方式

• OAI收割 [2]

内容类型

• 会议论文 [1]
• 期刊论文 [1]

发表日期

• 2019 [1]
• 2010 [1]

学科主题

筛选

浏览/检索结果: 共2条，第1-2条 帮助 条数/页： 5101520253035404550556065707580859095100 排序方式： 请选择题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序 Timing performance evaluation of Radio Determination Satellite Service (RDSS) for Beidou system 期刊论文  OAI收割 ACTA ASTRONAUTICA, 2019, 卷号: 156, 页码: 125-133 作者:  Wang, Dongxia;  Guo, Rui;  Zhang, Tianqiao;  Hu, Xiaogong   |  收藏  |  浏览/下载：53/0  |  提交时间：2019/05/23 Radio determination satellite service  One-way timing  Two-way timing  Performance evaluation   The design of acquisition circuit for grating digital signal based on FPGA (EI CONFERENCE) 会议论文  OAI收割 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China 作者:  Wang W.-G. 收藏  |  浏览/下载：42/0  |  提交时间：2013/03/25 In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to  counting circuit  the results show that the design method will help improve the controlled object of measurement precision and control accuracy. 2010 IEEE.  we design a circuit based on FPGA to realize multiplier  kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as filtering  multiplier kam-to and counting. The main function of filter circuit is to eliminate the jitter and noise interference existing in the quadrate encoder signals. Kam-to multiplier circuit can accurately judge the full cycle and half-cycle of incremental encoder  at the same time can make fourfold multiplier. Counting circuit can use IP cores owned by Quartus II which is not restricted on the median. At last  timing simulation based on Modelsim carried on the three modules