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	SRAM型FPGA在辐照环境下的容错技术研究学位论文 OAI收割中国科学院大学光电技术研究所: 中国科学院大学, 2019 作者: 薛晓良 \| 收藏 \| 浏览/下载：40/0 \| 提交时间：2019/06/26 Sram型fpga，virtex-5，配置ram，icap，seu，必要位，帧结构
	自定义FPGA测试系统的设计与应用期刊论文 OAI收割计算机测量与控制, 2012, 期号: 09, 页码: 2363-2365 作者: 宁永慧; 刘辉; 马天波收藏 \| 浏览/下载：20/0 \| 提交时间：2013/03/11 Virtex5测试系统软件测试并行处理
	雷达目标跟踪的粒子滤波算法研究及实现学位论文 OAI收割硕士: 中国科学院研究生院, 2010 叶斌丽收藏 \| 浏览/下载：51/0 \| 提交时间：2014/05/04 跟踪雷达非合作目标跟踪粒子滤波重采样 FPGA Virtex-5
	Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者: Wang Y.; Wang Y.; Wang Y.; Sun H.; Sun H. 收藏 \| 浏览/下载：43/0 \| 提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition these functions that adjustments of exposure beginning time integral time AOI (Area of Interest) output and so on are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip) and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate low power intelligent and miniaturization digital video camera.