中国科学院机构知识库网格系统: 检索

CMOS图象传感器IBIS5A应用设计 期刊论文 OAI收割
微计算机信息, 2011, 期号: 01, 页码: 74-75+202
作者: 刘金国; 王冶; 周怀得; 孔德柱; 李广泽

收藏 | 浏览/下载：19/0 | 提交时间：2013/03/11

Laser pulse coded signal frequency measuring device based on DSP and CPLD (EI CONFERENCE) 会议论文 OAI收割
International Symposium on Photoelectronic Detection and Imaging 2011: Laser Sensing and Imaging; and Biological and Medical Applications of Photonics Sensing and Imaging, May 24, 2011 - May 26, 2011, Beijing, China
作者: Zhang H.-B.; Wang T.-F.; Guo R.-H.; Li Y.; Li Y.

收藏 | 浏览/下载：38/0 | 提交时间：2013/03/25

Laser pulse code is an anti-jamming measures used in semi-active laser guided weapons. On account of the laser-guided signals adopting pulse coding mode and the weak signal processing it need complex calculations in the frequency measurement process according to the laser pulse code signal time correlation to meet the request in optoelectronic countermeasures in semi-active laser guided weapons. To ensure accurately completing frequency measurement in a short time it needed to carry out self-related process with the pulse arrival time series composed of pulse arrival time calculate the signal repetition period and then identify the letter type to achieve signal decoding from determining the time value number and rank number in a signal cycle by Using CPLD and DSP for signal processing chip designing a laser-guided signal frequency measurement in the pulse frequency measurement device improving the signal processing capability through the appropriate software algorithms. In this article we introduced the principle of frequency measurement of the device described the hardware components of the device the system works and software analyzed the impact of some system factors on the accuracy of the measurement. The experimental results indicated that this system improve the accuracy of the measurement under the premise of volume real-time anti-interference low power of the laser pulse frequency measuring device. The practicality of the design reliability has been demonstrated from the experimental point of view.

A new approach to realize UART (EI CONFERENCE) 会议论文 OAI收割
2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, August 12, 2011 - August 14, 2011, Harbin, China
作者: Wang Y.; Wang Y.; Wang Y.; Wang Y.; Wang Y.

收藏 | 浏览/下载：35/0 | 提交时间：2013/03/25

In order to connect DSP which has synchronous serial ports to the devices implementing asynchronous communications protocol a method to implement UART communications based on programmable logic device is proposed in the paper. In the proposed method the core function of UART is integrated in CPLD with VHDL. Firstly UART data frame format and operational principle of UART were introduced after reviewing some methods to realize UART. The methods to implement UART transmitter UART receiver and baudrate generator using VHDL were illustrated in detail. Then pre-simulation and synthesize of VHDL program were executed. Finally the test with bit error rate was carried out on physical system. Experimental results indicate that 75 percent of the GLB are used by UART and the bit error rate is less than 109. The experiment was implemented utilizing the RS-422 protocol and the baudrate is 62.5kb/s. The proposed method can satisfy the system requirements of high integration stabilization low bit error rate strong anti-jamming and low cost. 2011 IEEE.

Embedded system of time uniform based on DSP (EI CONFERENCE) 会议论文 OAI收割
2010 International Conference on Computer, Mechatronics, Control and Electronic Engineering, CMCE 2010, August 24, 2010 - August 26, 2010, Changchun, China
作者: Li N.; Liu C.-X.; Liu C.-X.; Chen J.; Guo L.-H.

收藏 | 浏览/下载：24/0 | 提交时间：2013/03/25

We introduced a design method of DSP-based System of time uniform which combine the GPS and the Compass to calibrate the time. The system can use UTC (Coordinated Universal Time) of the GPS or the Compass for time base to generate absolute time and different frequency of synchronous signals. We used DSP (Digital Signal Processor) to calculate the satellite information which includes the UTC time. After getting the UCT time information put it into the CPLD (Complex Programmable Logic Device) for correction of time delay and serialization to output. Meanwhile we divided 1PPS (one-pulse-per-second) signal of the GPS and the Compass into 20Hz 50Hz and 800Hz synchronous signal. And we analyzed the precision of time and frequency. To conclude the uncertainty of system absolute time is less than 100ns the uncertainty of system synchronous signals is less than 20ns. This system is easy and flexible for use stable and reliable in performance. 2010 IEEE.

基于CPLD的CCD信号发生器的研究 期刊论文 OAI收割
微计算机信息, 2009, 期号: 17
姜博; 阮锦

收藏 | 浏览/下载：24/0 | 提交时间：2012/09/25

CPLD D/A转换器 CCD 信号发生器

A sensitive solid-phase time-resolved fluorescence immunoassay apparatus (EI CONFERENCE) 会议论文 OAI收割
International Symposium on Photoelectronic Detection and Imaging 2009: Laser Sensing and Imaging, June 17, 2009 - June 19, 2009, Beijing, China
作者: Song K.-F.; Li J.-L.; Zhang W.-L.; Wang Y.-L.

收藏 | 浏览/下载：37/0 | 提交时间：2013/03/25

In the device a He-Ne laser of flash frequency 1-20 Hz was adopted as exciting light source and three key technical problems have been solved successfully in order to enhance the detecting sensitivity and measuring stability of the device for time-resolved fluorimmunoassays(TRFIA) [1]. The first one is to design optimum exciting optical system so that the exciting light beam excite the sample most effectively. The second one is to have a project spectrum filter which can reduce the affection of the background light to the photomultiplier tube and also ensure influence of the stray light and mixed diffusion light to the sample fluorescence to the least the sample fluorescence through the integrating sphere and come to the grating monochromator The right wavelength will be chosed through changing the angle of incidence of the grating monochromator. The third one is to simulate the principle of sample averaging of BOXCAR averager. In the device SCM was used as primary controller and CPLD was used as timing controller. Through the preparation process signal-to-noise ratio(SNR) will be improved also adjust delay time ampling frequency and sampling number arbitrarily. By testing the sensitivity is 10-12mol/L(substance marked by Eu3+) examination repeat is &le2.5% examination linearity is from 10 -8mol/L to 10-12mol/L correlation coefficient is 99.98%(p&le0.01). The instrument is advanced for ultrasensitive detection of antigen and antibody and solve the tumor genetic variation the virus protein detection. 2009 SPIE.

氢原子钟智能化监控系统 学位论文 OAI收割
硕士, 上海天文台: 中国科学院上海天文台, 2008
陈丛军

收藏 | 浏览/下载：50/3 | 提交时间：2011/07/01

氢原子钟监控系统 A/D转换器 CPLD 键盘 LCD显示器 FLASH数据存储器数字电位器恒温系统

Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE) 会议论文 OAI收割
2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China
作者: Sun H.; Wang Y.; Wang Y.; Wang Y.; Wang Y.

收藏 | 浏览/下载：31/0 | 提交时间：2013/03/25

CCD noises and their causes are analyzed. Methods to control these noises such as Correlated Double Sampling (CDS) filtering cooling clamping and calibration are proposed. To improve CCD sensor's performances the IC called Analog Front End (AFE) integration of CDS clamping Programmable Gain Amplifier (PGA) offset and ADC which can fulfill the CDS and analog-to-digital conversion is employed to process the output signal of CCD. Based on the noise control approaches the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator for both CCD and AFE and (2) interface helping to analysis and transfer control command and status information between MCU controller and drive pulse generator or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed such as clock generator for CCD and AFE MCU interface AFE serial interface output interface CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip Xilinx XC2C256-6-VQ100 with 20MHz pixel frequency and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last the design result is presented.

Real-time quality control on a smart camera (EI CONFERENCE) 会议论文 OAI收割
ICO20: Optical Information Processing, August 21, 2005 - August 26, 2005, Changchun, China
Xiao C.; Zhou H.; Li G.; Hao Z.

收藏 | 浏览/下载：29/0 | 提交时间：2013/03/25

A smart camera is composed of a video sensing high-level video processing communication and other affiliations within a single device. Such cameras are very important devices in quality control systems. This paper presents a prototyping development of a smart camera for quality control. The smart camera is divided to four parts: a CMOS sensor a digital signal processor (DSP) a CPLD and a display device. In order to improving the processing speed low-level and high-level video processing algorithms are discussed to the embedded DSP-based platforms. The algorithms can quickly and automatic detect productions' quality defaults. All algorithms are tested under a Matlab-based prototyping implementation and migrated to the smart camera. The smart camera prototype automatic processes the video data and streams the results of the video data to the display devices and control devices. Control signals are send to produce-line to adjust the producing state within the required real-time constrains.

Design and DSP implementation of star image acquisition and Star point fast acquiring tracking (EI CONFERENCE) 会议论文 OAI收割
2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 2, 2005 - November 5, 2005, Zian, China
作者: Wang X.; Wang X.; Wang X.

收藏 | 浏览/下载：22/0 | 提交时间：2013/03/25

Star sensor is a special high accuracy photoelectric sensor. Attitude acquisition time is an important function index of star sensor. In this paper the design target is to acquire 10 samples per second dynamic performance. On the basis of analyzing CCD signals timing and star image processing a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design the operation moving the data in expanded windows including the star to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. During the CCD saving the star image to memory DSP processes the data in the on-chip memory. This parallelism greatly improves the efficiency of processing. The scheme proposed here results in enormous savings of memory normally required. In the scheme DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The efficiency of processing is discussed in numerical tests. Only in 3.5ms is acquired the five lightest stars in the star acquisition stage. In 43us the data in five expanded windows including stars are moved into the internal memory of DSP and in 1.6ms five star coordinates are achieved in the star tracking stage.