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	Combustion characteristics of test and reserch on electronic control fuel injection system of cars GDI engine (EI CONFERENCE) 会议论文 OAI收割 2011 2nd International Conference on Mechanic Automation and Control Engineering, MACE 2011, July 15, 2011 - July 17, 2011, Inner Mongolia, China Zhao X.; Xiong W. 收藏 \| 浏览/下载：22/0 \| 提交时间：2013/03/25 A cars GDI engine electronic control fuel injection system has been developed for a GDI engine based on analysing the work principles of the control system of the engine in detail in this paper. The MCU produced by Freescale was chosen as the main controller of ECU(Electronic Control System) at the beginning then the fuel injection driving circuit module was designed fuel injection module programme was designed.The control system for different load and speed achieved flexible control precision flexible fast response which was proved by the engine test. This control system was proved to be ensure capability and performance of fuel injection demands. 2011 IEEE.
	Storage and compression design of high speed CCD (EI CONFERENCE) 会议论文 OAI收割 4th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 19, 2008 - November 21, 2008, Chengdu, China Cai X.; Zhai L. P. 收藏 \| 浏览/下载：58/0 \| 提交时间：2013/03/25 In current field of CCD measurement large area and high resolution CCD is used to obtain big measurement image so that speed and capacity of CCD requires high performance of later storage and process system. The paper discusses how to use SCSI hard disk to construct storage system and use DSPs and FPGA to realize image compression. As for storage subsystem Because CCD is divided into multiplex output SCSI array is used in RAID0 way. The storage system is composed of high speed buffer DMA controller control MCU SCSI protocol controller and SCSI hard disk. As for compression subsystem according to requirement of communication and monitor system the output is fixed resolution image and analog PAL signal. The compression means is JPEG2000 standard in which 9/7 wavelets in lifting format is used. 2 DSPs and FPGA are used to compose parallel compression system. The system is composed of FPGA pre-processing module DSP compression module video decoder module data buffer module and communication module. Firstly discrete wavelet transform and quantization is realized in FPGA. Secondly entropy coding and stream adaption is realized in DSPs. Last analog PAL signal is output by Video decoder. Data buffer is realized in synchronous dual-port RAM and state of subsystem is transfer to controller. Through subjective and objective evaluation the storage and compression system satisfies the requirement of system. 2009 SPIE.
	Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China 作者: Sun H.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：31/0 \| 提交时间：2013/03/25 CCD noises and their causes are analyzed. Methods to control these noises such as Correlated Double Sampling (CDS) filtering cooling clamping and calibration are proposed. To improve CCD sensor's performances the IC called Analog Front End (AFE) integration of CDS clamping Programmable Gain Amplifier (PGA) offset and ADC which can fulfill the CDS and analog-to-digital conversion is employed to process the output signal of CCD. Based on the noise control approaches the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator for both CCD and AFE and (2) interface helping to analysis and transfer control command and status information between MCU controller and drive pulse generator or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed such as clock generator for CCD and AFE MCU interface AFE serial interface output interface CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip Xilinx XC2C256-6-VQ100 with 20MHz pixel frequency and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last the design result is presented.