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	End-to-end learning interpolation for object tracking in low frame-rate video 期刊论文 OAI收割 IET Image Processing, 2020, 卷号: 14, 期号: 6, 页码: 1066-1072 作者: Liu, Liqiang; Cao, Jianzhong \| 收藏 \| 浏览/下载：71/0 \| 提交时间：2020/05/20 video signal processing learning (artificial intelligence) object tracking interpolation mobile computing low frame rates implicit video frame interpolation sub-network object tracking low frame-rate video high frame-rate latent video effective end-to-end optimisation frame rate tracking accuracy semantic video analytics end-to-end learning interpolation subsequent semantic analytics bandwidth constraints analytics performance
	Low complexity encoder optimization for HEVC 期刊论文 OAI收割 JOURNAL OF VISUAL COMMUNICATION AND IMAGE REPRESENTATION, 2016, 卷号: 35, 页码: 120-131 作者: Wang, Shanshe; Luo, Falei; Ma, Siwei; Zhang, Xiang; Wang, Shiqi \| 收藏 \| 浏览/下载：44/0 \| 提交时间：2019/12/13 HEVC Low complexity Intra mode decision CU splitting Reference frame selection Rate distortion optimization Video coding Encoder optimization
	Design of driving circuit for binocular CCD image system (EI CONFERENCE) 会议论文 OAI收割 5th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optoelectronic Materials and Devices for Detector, Imager, Display, and Energy Conversion Technology, April 26, 2010 - April 29, 2010, Dalian, China 作者: Zhang X.; Zhang X.; Zhang X. 收藏 \| 浏览/下载：48/0 \| 提交时间：2013/03/25 The paper designs a driving circuit of high sensitive wide dynamic and high signal-to-noise ratio for binocular CCD imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Inner structure and driving timing of the FTF5066M sensor are presented. Field Programmable Gate Array (FPGA) is used as the main device to accomplish the timing design of the circuits and power driver control of the two sensors. By using the Correlated Double Sampling (CDS) technique the video noise is reduced and the SNR of the system is increased. A 12- bit A/D converter is used to improve the image quality. The output rate of the imaging system designed with integrated chip can reach to 1.3 frames per second through bi-channel. For its good performance low power consumption and small volume the driving system can be applied to aeronautics and astronautics field. With a further improvement a maximum data output rate of 2.7 frames per second can be reached through all the eight channels of the two CCDs. 2010 Copyright SPIE - The International Society for Optical Engineering.
	Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者: Wang Y.; Wang Y.; Wang Y.; Sun H.; Sun H. 收藏 \| 浏览/下载：45/0 \| 提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition these functions that adjustments of exposure beginning time integral time AOI (Area of Interest) output and so on are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip) and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate low power intelligent and miniaturization digital video camera.