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	Communication synchronization in wireless optical link (EI CONFERENCE) 会议论文 OAI收割 2012 International Conference on Control Engineering and Communication Technology, ICCECT 2012, December 7, 2012 - December 9, 2012, Shenyang, Liaoning, China 作者: Guo J.; Guo J.; Wang H.; Wang H.; Wang H. 收藏 \| 浏览/下载：33/0 \| 提交时间：2013/03/25 An FPGA based transceiving synchronization method is demonstrated for Free Space Optical (FSO) communication system which is discussed separately as the transmitting protocol and the receiving protocol. During the discussion of these two parts the co-operation of them is also discussed. The transmitting protocol interfaces the outer input data with a parallel port buffers the input data encodes the input data stream serializes the parallel data and outputs the serialized data. It also has an output management unit to manage the activity of each part of the transmitting protocol. The receiving protocol filters and synchronizes the input serial data stream parallels the serial data stream decodes the input data checks received error handles transmission exception and interfaces the outer receiver with a parallel port. The entire transceiving protocol could be programmed into a single FPGA chip to improve system integrity and reduce the system cost. The presented protocol could be taken as "protocol transparent" for outer interfaces meaning that when interfacing the presented system to an outer system users don't have to consider what protocol the outer system transceiving data stream is under for example the TCP/IP protocol or anything else in the case that its I/O interface is a parallel port. Simulation and final experiment prove that the protocol presented is a working solution at a certain bit rate scale. 2012 IEEE.
	The sequence measurement system of the IR camera (EI CONFERENCE) 会议论文 OAI收割 International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Infrared Imaging and Applications, May 24, 2011 - May 24, 2011, Beijing, China 作者: Zhang H.-B.; Han H.-X.; Geng A.-H. 收藏 \| 浏览/下载：39/0 \| 提交时间：2013/03/25 Currently the IR cameras are broadly used in the optic-electronic tracking optic-electronic measuring fire control and optic-electronic countermeasure field but the output sequence of the most presently applied IR cameras in the project is complex and the giving sequence documents from the leave factory are not detailed. Aiming at the requirement that the continuous image transmission and image procession system need the detailed sequence of the IR cameras the sequence measurement system of the IR camera is designed and the detailed sequence measurement way of the applied IR camera is carried out. The FPGA programming combined with the SignalTap online observation way has been applied in the sequence measurement system and the precise sequence of the IR camera's output signal has been achieved the detailed document of the IR camera has been supplied to the continuous image transmission system image processing system and etc. The sequence measurement system of the IR camera includes CameraLink input interface part LVDS input interface part FPGA part CameraLink output interface part and etc thereinto the FPGA part is the key composed part in the sequence measurement system. Both the video signal of the CmaeraLink style and the video signal of LVDS style can be accepted by the sequence measurement system and because the image processing card and image memory card always use the CameraLink interface as its input interface style the output signal style of the sequence measurement system has been designed into CameraLink interface. The sequence measurement system does the IR camera's sequence measurement work and meanwhile does the interface transmission work to some cameras. Inside the FPGA of the sequence measurement system the sequence measurement program the pixel clock modification the SignalTap file configuration and the SignalTap online observation has been integrated to realize the precise measurement to the IR camera. Te sequence measurement program written by the verilog language combining the SignalTap tool on line observation can count the line numbers in one frame pixel numbers in one line and meanwhile account the line offset and row offset of the image. Aiming at the complex sequence of the IR camera's output signal the sequence measurement system of the IR camera accurately measures the sequence of the project applied camera supplies the detailed sequence document to the continuous system such as image processing system and image transmission system and gives out the concrete parameters of the fval lval pixclk line offset and row offset. The experiment shows that the sequence measurement system of the IR camera can get the precise sequence measurement result and works stably laying foundation for the continuous system. 2011 Copyright Society of Photo-Optical Instrumentation Engineers (SPIE).
	808nm high-power semiconductor laser therapeutic apparatus based on LPC2138 (EI CONFERENCE) 会议论文 OAI收割 2011 IEEE International conference on Intelligent Computation and Bio-Medical Instrumentation, ICBMI 2011, December 14, 2011 - December 17, 2011, Wuhan, Hubei, China 作者: Wang B.; Wang B. 收藏 \| 浏览/下载：37/0 \| 提交时间：2013/03/25 In this paper we designed an intelligent 808nm high-power semiconductor laser therapeutic apparatus with the LPC2138 ARM processor. The laser is driven by the digital constant current source module and the apparatus has good human-machine interaction performance on account of set the parameters intelligently. The function such as operation mode output power output pulse width and pulse cycle could be easily set through the TFT touch screen. The application software could transmission the log data to the computer by the USB interface in order to check and study the records later. 2011 IEEE.
	Transceiving protocol designc for a free space optical communication system (EI CONFERENCE) 会议论文 OAI收割 2008 International Conference on Optical Instruments and Technology: Optical Systems and Optoelectronic Instruments, November 16, 2008 - November 19, 2008, Beijing, China Hualong W.; Wanxin S.; Zhongbao X. 收藏 \| 浏览/下载：61/0 \| 提交时间：2013/03/25 A new transceiving protocol is demonstrated for a Free Space Optical (FSO) communication system and it's discussed in two parts: the transmitting protocol and the receiving protocol. During the discussion of these two parts the cooperation of them is also discussed. Different from wired communication an FSO system modulates the data on a narrow beam of laser transmitting through the free space or the atmosphere and the protocol presented in this paper is mainly optimized for terrestrial Free Space Optical links in which the signal channel of the system is mainly the atmosphere. Due to the complex composition and activity of the atmosphere this signal channel brings in great influence on the transmitting laser in it for example the absorption and scattering of the atmosphere molecules and aerosols the scintillation of received laser power caused by the turbulence of the atmosphere all of which results in a much higher Bit Error Rate (BER) of the communication system. Thus in designing a protocol for an FSO system more effort should be taken in the encoding of the data stream the synchronization of the data stream error checking and exception handling. The main function of the transmitting protocol includes interfacing the outer input data with a parallel port buffering the input data encoding the input data stream serializing the parallel data and output the serialized data. It also has an output management unit to manage the activity of each part of the transmitting protocol. The main function of the receiving protocol includes filtering and synchronizing the input serial data stream paralleling the serial data stream decoding the input data error checking exception handling and interfacing the outer receiver with a parallel port. The entire transceiving protocol could be programmed into a single FPGA chip to improve system integrity and reduce the system cost. The presented protocol could be taken as "protocol transparent" for outer interfaces meaning that when interfacing the presented system to an outer system you don't have to consider what protocol the outer system transceiving data stream is under for example the TCP/IP protocol or anything else in the case that its I/O interface is a parallel port. Simulation and final experiment prove that the protocol presented is working fine at a certain bit rate scale. 2009 SPIE.
	Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者: Wang Y.; Wang Y.; Wang Y.; Sun H.; Sun H. 收藏 \| 浏览/下载：42/0 \| 提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition these functions that adjustments of exposure beginning time integral time AOI (Area of Interest) output and so on are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip) and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate low power intelligent and miniaturization digital video camera.
	Chip design of linear CCD drive pulse generator and control interface (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies - Advanced Optical Manufacturing and Testing Technologies, November 2, 2005 - November 5, 2005, Xian, China 作者: Sun H.; Wang Y.; Wang Y.; Wang Y.; Wang Y. 收藏 \| 浏览/下载：33/0 \| 提交时间：2013/03/25 CCD noises and their causes are analyzed. Methods to control these noises such as Correlated Double Sampling (CDS) filtering cooling clamping and calibration are proposed. To improve CCD sensor's performances the IC called Analog Front End (AFE) integration of CDS clamping Programmable Gain Amplifier (PGA) offset and ADC which can fulfill the CDS and analog-to-digital conversion is employed to process the output signal of CCD. Based on the noise control approaches the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator for both CCD and AFE and (2) interface helping to analysis and transfer control command and status information between MCU controller and drive pulse generator or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed such as clock generator for CCD and AFE MCU interface AFE serial interface output interface CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip Xilinx XC2C256-6-VQ100 with 20MHz pixel frequency and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last the design result is presented.