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	DyPipe: A Holistic Approach to Accelerating Dynamic Neural Networks with Dynamic Pipelining 期刊论文 OAI收割 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2023, 卷号: 38, 期号: 4, 页码: 899-910 作者: Zhuang, Yi-Min; Hu, Xing; Chen, Xiao-Bing; Zhi, Tian \| 收藏 \| 浏览/下载：10/0 \| 提交时间：2024/05/20 dynamic neural network (NN) deep neural network (DNN) accelerator dynamic pipelining
	GPU中流多处理器设计技术学位论文 OAI收割工程硕士, 中国科学院自动化研究所: 中国科学院大学, 2015 王骏也收藏 \| 浏览/下载：117/0 \| 提交时间：2015/09/02 GPU 流多处理器流水线指令系统仿真验证 GPU Streaming Multiprocessors pipelining instruction set simulation
	The application of TMS320c64x DSP assembly language in correlation tracking algorithms (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Congress on Image and Signal Processing, CISP 2010, October 16, 2010 - October 18, 2010, Yantai, China Huang D.; Wu Z.; Liang M.; Dong Y.; Peng T. 收藏 \| 浏览/下载：25/0 \| 提交时间：2013/03/25 In order to improve the real-time performance of the conventional correlation tracking algorithm based on full search method for its huge computation amount and vast correlation matching times in the process of searching an optimal matching position a method of combining the TMS320C64x DSP assembly language and software pipelining is proposed to realize template matching which costs the most time of the algorithm. Choose high performance DSP chip TMS320DM642 as the core processor of the hardware platform and schedule each one of the instruction in the algorithm to maximize performance using the instruction-level parallelism of the DSP. The experimental results indicate the time of template image matching implemented in assembly language has decreased from 49.36ms to 0.62ms. It is concluded that the correlation tracking adopting proposed method can meet the real-time and stability requirement of the target tracking. 2010 IEEE.
	Design of image nonuniformity correction and real-time record for CMOS camera (EI CONFERENCE) 会议论文 OAI收割 9th International Conference on Electronic Measurement and Instruments, ICEMI 2009, August 16, 2009 - August 19, 2009, Beijing, China Huilong Y.; Xin H.; Zhonghui W.; Donghe W. 收藏 \| 浏览/下载：25/0 \| 提交时间：2013/03/25 A configurable record capacity extensible and nonuniformity reducible of high speed camera is designed in this paper. The CMOS image sensor lupa-300 which is produced by Cypress Corporation is used for the system. There is nonuniformity existed in the sensor. The two point method of the image with real time correction algorithm has applied to process the image nonuniformity. Then the corrected image is storied into the NandFlash array. To improve the record speed and extend record capacity the pipelining and parallel bus mechanism is adopted. The experiment which is based on hardware platform indicates the camera can take about 250f/s at a resolution of 640*480 the consistent storage speed is up to 614.4 Mb/s consistent transmit from flash to Camera Link speed up to 1.093Gb/s.The system record time is up to 18.6 minutes. 2009 IEEE.