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	The design of acquisition circuit for grating digital signal based on FPGA (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China 作者: Wang W.-G. 收藏 \| 浏览/下载：45/0 \| 提交时间：2013/03/25 In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to counting circuit the results show that the design method will help improve the controlled object of measurement precision and control accuracy. 2010 IEEE. we design a circuit based on FPGA to realize multiplier kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as filtering multiplier kam-to and counting. The main function of filter circuit is to eliminate the jitter and noise interference existing in the quadrate encoder signals. Kam-to multiplier circuit can accurately judge the full cycle and half-cycle of incremental encoder at the same time can make fourfold multiplier. Counting circuit can use IP cores owned by Quartus II which is not restricted on the median. At last timing simulation based on Modelsim carried on the three modules
	An efficient discrete particle swarm algorithm for task assignment problems (EI CONFERENCE) 会议论文 OAI收割 2009 IEEE International Conference on Granular Computing, GRC 2009, August 17, 2009 - August 19, 2009, Nanchang, China 作者: Wang C. 收藏 \| 浏览/下载：18/0 \| 提交时间：2013/03/25 Task Assignment Problems (TAPs) in distributed computer system are general NP-hard and usually modeled as integer programming discrete problems. Many algorithms are proposed to resolve those problems. Discrete particle swarm algorithm (DPS) is a newly developed method to solve constraint satisfaction problem (CSP) which has advantage on search capacity and can find more solutions. We proposed an improved DPS to solve TAP in this paper. DPS has a special operator namely coefficient multiplying speed which is designed for CSP but does not exist in other discrete problems. Thus we redefined a coefficient multiplying speed operator with probability selection. We analyzed the speed and position updating formula then we derived a refined position updating formula. Several experiments are carried out to test our DPS. Experimental results show that our algorithm has more efficient search capacity higher success rate less running time and more robust.
	Static properties of a femtosecond electron diffraction system 期刊论文 OAI收割 acta physica sinica, 2006, 卷号: 55, 期号: 12, 页码: 6500-6505 作者: Liu Yun-Quan; Liang Wen-Xi 收藏 \| 浏览/下载：25/0 \| 提交时间：2015/08/18 femtosecond electron diffraction deflection sensitivity time-resolve spatial-resolve
	Design of an improved data signal timing for an amorphous silicon active-matrix organic LED display (EI CONFERENCE) 会议论文 OAI收割 ICO20: Display Devices and Systems, August 21, 2005 - August 26, 2005, Changchun, China 作者: Zhang Z.-W. 收藏 \| 浏览/下载：26/0 \| 提交时间：2013/03/25 The most critical issue in the design of an active matrix organic light emitting diode (AM-OLED) display pixel is the pixel to the pixel luminance uniformity. By substituting four-thin film transistor (TFT) pixel circuit for two-TFT pixel circuit the luminous uniformity has great improved but it requires more components than the two-TFT pixel circuit. There are some barriers needed to resolve to utilize hydrogenated amorphous silicon transistor to lit OLED such as low field effect mobility low output current and threshold voltage shift. In this article a two-a-Si:H TFT pixel circuit was designed which consisted of one named switching TFT and the other named driving TFT. The driving TFT gate line structure modified and a data signal timing improved were reported. The modified driving TFT can provide enough current about 30 microampere to lit OLED and the novel data signal timing can provide a constant current to OLED by restraining the driving TFT threshold voltage variation. In the novel data signal timing the control signals to the driving TFT gate include a data signal and a reverse data signal. The signals alteration is performed either at a frame rate or at a line rate. By experiments the driving TFT output current value is plotted as a function of the time in different reversed voltage value. When the magnitude of the positive data signal and the negative data signal is equal the variety of Vth is smallest about 1.28V after a fixed stressing time of 1.33104min which shows the novel data signal timing can improved the driving TFT output-input current stability.