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	GNSS Timing Performance Assessment and Results Analysis 期刊论文 OAI收割 SENSORS, 2022, 卷号: 22, 期号: 7, 页码: 10 作者: Zhu, Lin; Zhang, Huijun; Li, Xiaohui; Zhu, Feng; Liu, Yinhua \| 收藏 \| 浏览/下载：37/0 \| 提交时间：2022/08/15 GNSS timing performance time transfer accuracy assessment
	Optimal Weighting Method for Reducing Digital Satellite TV Differential Timing Error 期刊论文 OAI收割 CHINESE JOURNAL OF ELECTRONICS, 2020, 卷号: 29, 期号: 2, 页码: 322-326 作者: Wang, Shanhe; Hua, Yu; Xiang, Yu; Huang, Changjiang; Gao, Yuanyuan \| 收藏 \| 浏览/下载：42/0 \| 提交时间：2020/09/01 Digital satellite TV differential timing (DSTVDT) Satellite ephemeris error Timing accuracy Optimal weighting method
	Research of the navigation accuracy for the X-ray pulsar navigation system 期刊论文 OAI收割 acta physica sinica, 2012, 卷号: 61, 期号: 20 作者: Wang Peng; Zhao Bao-Sheng; Sheng Li-Zhi; Hu Hui-Jun; Yan Qiu-Rong 收藏 \| 浏览/下载：28/0 \| 提交时间：2015/07/01 detectors X-ray pulsar navigation timing accuracy dead time
	The design of acquisition circuit for grating digital signal based on FPGA (EI CONFERENCE) 会议论文 OAI收割 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China 作者: Wang W.-G. 收藏 \| 浏览/下载：37/0 \| 提交时间：2013/03/25 In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to counting circuit the results show that the design method will help improve the controlled object of measurement precision and control accuracy. 2010 IEEE. we design a circuit based on FPGA to realize multiplier kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as filtering multiplier kam-to and counting. The main function of filter circuit is to eliminate the jitter and noise interference existing in the quadrate encoder signals. Kam-to multiplier circuit can accurately judge the full cycle and half-cycle of incremental encoder at the same time can make fourfold multiplier. Counting circuit can use IP cores owned by Quartus II which is not restricted on the median. At last timing simulation based on Modelsim carried on the three modules
	Design and DSP implementation of star image acquisition and Star point fast acquiring tracking (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 2, 2005 - November 5, 2005, Zian, China 作者: Wang X.; Wang X.; Wang X. 收藏 \| 浏览/下载：22/0 \| 提交时间：2013/03/25 Star sensor is a special high accuracy photoelectric sensor. Attitude acquisition time is an important function index of star sensor. In this paper the design target is to acquire 10 samples per second dynamic performance. On the basis of analyzing CCD signals timing and star image processing a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design the operation moving the data in expanded windows including the star to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. During the CCD saving the star image to memory DSP processes the data in the on-chip memory. This parallelism greatly improves the efficiency of processing. The scheme proposed here results in enormous savings of memory normally required. In the scheme DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The efficiency of processing is discussed in numerical tests. Only in 3.5ms is acquired the five lightest stars in the star acquisition stage. In 43us the data in five expanded windows including stars are moved into the internal memory of DSP and in 1.6ms five star coordinates are achieved in the star tracking stage.